W-Band Silicon-Based Frequency Synthesizers Using Injection-Locked and Harmonic Triplers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 1 dB with respect to a 20.2-GHz input. The 0 3 0 3 mm 2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply. Index Terms-Frequency tripler, injection-locked, millimeterwave, quadrature voltage-controlled oscillator, regenerative peaking, wide locking range. I. INTRODUCTION E XCITING new opportunities are envisioned for silicon integrated circuits that are capable of mm-wave operation. Potential consumer applications include: gigabit per second short-range wireless communication in the 60-GHz (defined in the IEEE 802.15.3c standard) and 120-GHz bands, long-range collision avoidance radar for automobiles at 77 and 79 GHz, and sub-terahertz imaging (94 GHz and above) [1]-[3]. Production silicon VLSI technologies have demonstrated a peak transit frequency, , above 200 GHz for bipolar (NPN) devices [4], [5] and higher than 300 GHz for CMOS (NFET) transistors [6], [7], which has focused commercial interest towards millimeter-wave (mm-wave) frequency applications for silicon integrated circuits. Implementation of mm-wave transceivers in baseline CMOS technology is attractive because of its high potential for both low cost in volume production and RF/baseband co-integration. Single-sideband modulation or demodulation in a mm-wave transceiver requires a mm-wave local oscillator (LO) with quadrature (i.e., I and Q) outputs. A phase and amplitude tuning mechanism with about 5 and 0.5 dB [8] of correction range is required in order to tune out the unwanted sideband, as sideband rejection is often degraded by phase and amplitude

Progress In Electromagnetics Research C, 2014

In this paper, a 42 GHz frequency synthesizer fabricated with 0.13 µm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic (CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base structure is used in the frequency doubler design to widen the bandwidth and improve the fundamental rejection. The doubler shows a 41% fractional 3 dB bandwidths with a fundamental rejection better than 25.7 dB. The synthesizer has a maximum output power of 0 dBm with a DC power consumption of 60 mW. The worst phase noise at 100 kHz, 1 MHz and 10 MHz offset frequencies from the carrier is −71 dBc/Hz, −83 dBc/Hz and −102.4 dBc/Hz, respectively.

IEEE Journal of Solid-State Circuits, 2004

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as 70 dBc and the phase noise is lower than 116 dBc/Hz at 1 MHz over the whole tuning range.

2010

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. The 20GHz PLL generates a signal with a phase noise as low as −106dBc/Hz using tail feedback to improve the phase noise. The proposed 60GHz ILO uses a combination of parallel and tail injection to enhance the locking range by reducing the Injection Locked Oscillator (ILO) current at the moment of injection. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of −96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply. To to author's knowledge this phase noise is about 20dB better then recently reported QPLL and about 10dB compared to differential PLL operating at similar frequency.

International Journal of Electronics and Electrical Engineering, 2014

A 1.1GHz phase-locked loop frequency synthesizer has been developed, designed and fabricated to study phase noise (PN) of the system. The system has been implemented by using a frequency synthesizer (ADF4002, Analog Devices), having a low noise digital phase frequency detector, a precision charge pump, a programmable reference divider (R divider) and a programmable feedback frequency divider (N divider). The charge pump, reference divider and phase frequency divider are programmed externally through a serial peripheral interface by writing to CLOCK, DATA and LATCH ENABLE control of the device. The system is interfaced to a personnel computer through an 8085 microprocessor via RS232 serial bus. This paper will give a brief outline of the hardware design, testing and study the PN of the system.  Index Terms-phase-locked loop, loop filter, phase noise, OshonSoft Tulshi Bezboruah received the B.Sc. degree in physics with electronics from the University of Dibrugarh, India, in 1990 and the M.Sc. and Ph.D. degrees in electronics and radio physics from the

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.

The design and simulation of a 1.35 GHz CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based in a wideband PLL topology with a high frequency reference, giving as result low phase noise, fast switching time, a low divider ratio and a reduction in the chip area. Besides, the use of a novel charge-pump circuit with positive feedback and current reuse allows a further reduction in both, chip area and power consumption, making the structure desirable for high-frequency low-voltage phase-locked loops.

IEEE Journal of Solid-State Circuits, 2019

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28-31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than −40 dBc. The active silicon area was 0.32 mm 2 , and the total power consumption was 41.8 mW.

Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009

This paper presents a low-power/low-voltage frequency synthesizer for the frequency of 2.4 GHz, which were designed and fabricated in a standard 0.18 Pm CMOS process. This synthesizer is based on a Phase-locked Loop (PLL) with a integer divider in the feedback loop and for a voltage supply of only 1.8 V, it presents a total power consumption of 3.4 mW. The power consumptions for the Voltage-controlled oscillator, phase-frequency difference/charge-pump and for the divider are 2 mW, 1 mW, 420 PW, respectively. The PLL is very fast, e.g., it takes only 1.6 Ps to lock, which makes it a perfect companion for devices where frequency hops must be done very quickly.

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003

In this paper, we present a 10/30 CHz MMIC tripler using a 0.35 pm, 60 GHafMAx BiCMOS SiCe technology. It exhibits a conversion gain in the-5 dB range, a fundamental rejection between-12 and-24 dB over an input dynamic range of 1-5; 31 dBm. A low additive phase noise of-143 dBcJHz at a frequency offset of 100 kHz is anticipated. The DC power consumption is 440 mW. The chip surface i s 800x650 pm' (0.4 mm2 only without the probe pads area). In order to drive this tripler, the design of a MMIC SiCe Xband VCO and its measured performance (0.8 GHz tuning range,-5 dBm output power and-87 dBc/Hz phase noise @ 100 kHz off carrier) is also reported. I.

2007

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase-locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in integrated-circuit design, the book will also be of interest to researchers and graduate students in electrical engineering.

IEEE Journal of Solid-State Circuits, 2002

A 2.5-GHz/900-MHz dual fractional-/integerfrequency synthesizer is implemented in 0.35-m 25-GHz BiCMOS. A 16 fractional-synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip 16 modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of 88 dBc/Hz for 2.47-GHz output frequency and 98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply.

IEEE Transactions on Microwave Theory and Techniques, 2000

IEEE Journal of Solid-State Circuits, 2000

A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-m SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic range (SFDR) of the DDFS is better than 48 dBc at low synthesized frequencies, decreasing to 45.7 dBc worst case at the Nyquist synthesized frequency for output frequency band (0-2.5 GHz). The DDFS consumes 460 mW at a 3.3-V supply and achieves a high power efficiency figure of merit (FOM) of 10.87 GHz/W. The chip occupies mm .

Analog Integrated Circuits and Signal Processing, 2016

A highly linear and fully-integrated frequencymodulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57-64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (RD) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than −80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is 2:04 mm 2 , and the total power consumption is 280 mW.

Proceedings of the Int …, 2006

Due to development of both wireless communication users and communication line users, utilization of high-speed communications has become a vital essence. High speed digital microwave radios have a great contribution in wireless telecommunications. Having a different and high capacitance, these radios can transmit and receive data in point to point links in far distances up to 30 km. Considering the high rate of utilization such digital microwave radios have in lower bands, it is imperative to utilize such kind of radios in upper bandsfor accessing more channels. One of the radios that plays a significant role in communications is digital microwave radio 18 GHz. Through using a proper modulation in this band, transmitting data with high rate is achievable. In this paper, frequency synthesizer of this radio has been analyzed, designed and implemented. By applying proper changes, this synthesizer can be used as a frequency sweeper either. In this project in order to have a stable local oscillator and a good phase noise of output signal, a phase locked DRO was designed and implemented. This stable signal will be mixed with an L-band synthesized signal and it will generate signal in the band 17.7 GHz -19.7 GHz with step 0.25 MHz. The stable output signal of this synthesizer has a very good phase noise at 18 GHz. We have achieved to phase noise up to -88 dBc/Hz @10 kHz in 18 GHz which is a proper phase noise for using different modulations such as QPSK, 16QAM, 64QAM and...