Polar Quantizer for Wireless Receivers: Theory, Analysis, and CMOS Implementation

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal envelope. Compared to a digital-quadrature TX architecture this results in a significantly reduced average and peak RF-DAC cell utilization. Therefore, the RF-DAC can be operated in less backoff at higher average output power and drain efficiency. The phase modulation is constrained in order to relax the phase modulators system requirements. Compared to a digital polar TX architecture utilizing an RF digital phase-locked loop with two-point phase modulation, this results in reduced frequency modulation and digital-controlled oscillator tuning range requirements. In addition, the design effort is further shifted from analog to digital domain in order to better exploit the benefits of CMOS technology scaling. Index Terms-Wireless communication, digital polar transmitter, digital quadrature transmitter, hybrid polar-I/Q transmitter, phase modulation, quadrature modulation, RF digital-to-analog converter (RF-DAC), RF digital power amplifier (RF-DPA), RF digital phase-locked loop (RF-DPLL). I. INTRODUCTION W IRELESS transceivers for multi-band, multi-standard mobile handset applications operating in the sub-6 GHz range are usually implemented in ultra-deep

IEEE Journal of Solid-State Circuits, 1997

We present a parallel analog vector quantizer (VQ) in 2.0-m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16 2 16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic template storage measures 60 2 78 m 2 . The output code is produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-delay product, independent of input levels and scale. Experimental results demonstrate 34 dB analog input dynamic range and 0.7 mW power dissipation at 3 s cycle.

2002

A S CMOS technologies continue to enjoy the bene ts of aggressive scaling, they become increasingly attractive for use in wireless receivers. Peak device f T 's on the order of 15GHz are available with 0.5m CMOS devices, making possible CMOS implementations of radio receivers in the 1-2GHz frequency range. One wireless system in this range that is particularly amenable to integration is a Global Positioning System GPS, whose signals are at 1.57542GHz. vii Finally, I must reserve the most special thanks for my friends and family, who have enriched my life in so many w a ys. I thank my undergraduate advisor, Dr. John Choma, Jr. of USC for his mentorship and his encouragement to pursue graduate work. I thank my many friends at Stanford and elsewhere for their support and friendship. Among those that I have not already mentioned are

IEEE Open Journal of the Communications Society, 2020

This paper studies optimum detectors and error rate analysis for wireless systems with low-resolution quantizers in the presence of fading and noise. A universal lower bound on the average symbol error probability (SEP), correct for all M-ary modulation schemes, is obtained when the number of quantization bits is not enough to resolve M signal points. In the special case of M-ary phase shift keying (M-PSK), the maximum likelihood detector is derived. Utilizing the structure of the derived detector, a general average SEP expression for M-PSK modulation with n-bit quantization is obtained when the wireless channel is subject to fading with a circularly-symmetric distribution. For the Nakagami-m fading, it is shown that a transceiver architecture with n-bit quantization is asymptotically optimum in terms of communication reliability if n ≥ log 2 M + 1. That is, the decay exponent for the average SEP is the same and equal to m with infinite-bit and n-bit quantizers for n ≥ log 2 M + 1. On the other hand, it is only equal to 1 2 and 0 for n = log 2 M and n < log 2 M, respectively. An extensive simulation study is performed to illustrate the accuracy of the derived results, energy efficiency gains obtained by means of low-resolution quantizers, performance comparison of phase modulated systems with independent in-phase and quadrature channel quantization and robustness of the derived results under channel estimation errors. INDEX TERMS Low-resolution ADCs, maximum likelihood detectors, symbol error probability, diversity order.

IEEE Signal Processing Letters, 2000

In this letter, in order to outperform the existing method for unrestricted polar quantizer (UPQ) design in terms of signal to quantization noise ratio, the asymptotic approximations of Rayleigh distributed function are applied to all magnitude regions of the UPQ, except to the last one. Given the constraint, the UPQ is designed to provide the minimum of the asymptotic mean-squared error distortion for the Gaussian source of unit variance. The effects of this constraint are studied for different bit rates . The accuracy of the derived formulas is assessed and the reasonable accuracy is observed for bit/sample.

IEEE Open Journal of the Solid-State Circuits Society

A power-scalable RF front-end using quantized analog signal processing is presented. The front-end is based on a voltage-mode power-scalable approach which allows the power dissipation to be scaled upon the operative scenario and to perform an agile calibration for mismatch impairments. Power and input dynamic range can be scaled upon the desired 1-dB compression point (1dBCP) (from −15.3 to 0.5 dBm) while keeping the same sensitivity with 2.5-dB NF. Signal path power can vary between 3.3 and 6.4 mW while clock generation and distribution power can vary between 1.6 and 18.5 mW/GHz, with a phase noise as low as −171.2 dBc/Hz. After calibration, IM2 and IM3 improved up to 33 dB while 1dBCP improved by 1 dB, which resulted in achieving an IIP3 of 26.1 dBm and IIP2 of 71 dBm at 0-dBm 1dBCP. INDEX TERMS Digital calibration, dynamic range (DR), high linearity, low power, nonuniform quantization, power scalable, quantized analog (QA), surface acoustic wave (SAW)-less, voltage-mode. I. INTRODUCTION T HE REMOVAL of surface acoustic wave (SAW) filters on the modern RF front-end has become a popular trend to reduce the overall cost and save precious realestate on the device [1], [2], [3], [4], [5], [6]. However, lack of high-Q filters demands high dynamic range (DR) from the RF front-end as well as requiring low noise floor even when large blockers are present (which generally is the case for SAW-less receivers). Large power consumption in both signal and local oscillator (LO) paths are needed to meet these stringent requirements. In modern RF front-ends, the gain in the signal path is limited by using the current-mode approach to increase input 1-dB compression point (1dBCP). This solution however requires a transimpedance amplifier (TIA) in the baseband, whose power can grow significantly when low input-referred noise and high compression point are demanded. In the LO path, the phase noise (PN) must be limited to reduce the impact of reciprocal mixing when large blockers are present. This can only be achieved by increasing the clock buffer sizes and consume significantly more power (e.g., 33 mW/GHz to get a PN as low as −170 dBc/Hz [7]). A. STATE-OF-THE-ART SAW-LESS RF RECEIVERS REVIEW Voltage-mode circuits have been widely implemented in RF front-end in the past. However, after the introduction of current passive mixers, which are technology-scaling friendly and are more compatible with modern low-voltage supplies [8], current-mode approaches have become the de-facto standard, especially in SAW-less applications. As mentioned previously, one of the major advantages of using the currentmode approach is minimization of the output swing which, in turn, increases the upper limit of the DR. Nevertheless, current-mode front-ends need power hungry TIAs with stringent noise requirements due to the inherent lack of RF gain in front of them. Fig. 2 provides state-of-the-art RF receivers as well as an overview of their performance and power dissipation breakdown (power consumption is reported for a common operative carrier at 2 GHz). While the majority of

arXiv (Cornell University), 2012

Future communication system requires large bandwidths to achieve high data rates, thus rendering analog-to-digital conversion (ADC) a bottleneck due to its high power consumption. In this paper, we consider monobit receivers for QPSK. The optimal monobit receiver under Nyquist sampling is obtained and its performance is analyzed. Then, a suboptimal but low-complexity receiver is proposed. The effect of imbalances between In-phase (I) and Quadrature (Q) branches is carefully examined. To combat the performance loss due to IQ imbalances, monobit receivers based on double training sequences and eight-sector phase quantization [14] are proposed. Numerical simulations show that the low-complexity suboptimal receiver suffers 3dB signal-to-noise-ratio (SNR) loss in additive white Gaussian noise (AWGN) channels and only 1dB SNR loss in multipath channels compared with matchedfilter monobit receiver with perfect channel state information (CSI). It is further demonstrated that the amplitude imbalance has essentially no effect on monobit receivers. In AWGN channels, receivers based on double training sequences can efficiently compensate for the SNR loss without complexity increase, while receivers with eight-sector phase quantization can almost completely eliminate the SNR loss caused by IQ imbalances. In dense multipath channels, the effect of imbalances on monobit receivers is slight.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

In this paper, new receiver concepts and CMOS circuits for future wireless communications applications are introduced. The concepts derived are applied to a few classes of wireless communications standards that are broad-band at radio frequencies and/or require a broad-band baseband circuitry. Multimode multiband operation and adaptivity as key requirements for future generation receivers are highlighted throughout the paper. The tradeoffs between power consumption, noise figure and linearity performance of low-noise amplifiers, mixers, and intermediate frequency filters are considered too.

Drug Discovery Today, 2000

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should reconcile a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 μm digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s. The transmitter section is designed for 0 dBm output power under the minimum 1 V supply, with a global efficiency higher than 15%.

2005

A quantized analog delay is designed as a requirement for the autocorrelation function in the Quadrature Downconversion Autocorrelation Receiver (QDAR) [1]. The quantized analog delay is comprised of a quantizer, multiple binary delay lines and an adder circuit. Being the foremost element, the quantizer consists of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to binary delay lines, which are a cascade of synchronized D-latches. The outputs available at each line are linked together to reconstruct the incoming signal using an adder circuit. For a delay time of 550 ps, simulation results in IBM's CMOS 0.12 μm technology show that the quantized analog delay requires a total current of 36.7 mA at a 1.6 V power supply. Furthermore, delays in the range of several nanoseconds are feasible at the expense of power. After a Monte Carlo simulation it becomes evident that the response of the quantized analog delay does not suffer drastically from neither process nor component mismatch variations.

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

IEEE Journal of Solid-State Circuits, 2021

A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3-to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2-4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of 430 µW is achieved for packets compatible with legacy pulseposition-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.

2010

In this paper, two different VCO-Based quantizers architectures are implemented and compared as multi-bit quantizers of Continuous-Time (CT) Sigma-Delta (Σ∆) modulator. The first one is the voltage-to-frequency while the second is the voltage-to-phase architecture. Two 4 th order CT-Σ∆ modulators are designed with Voltage-to-frequency and voltage-tophase quantizers respectively. Both modulators are designed and simulated in 0.13µm technology. The comparision shows that voltage-to-phase quantizer remarkably reduces the VCO nonlinearity and increases the modulator's maximum SNR .

In this paper, a noise analysis of a modulated quantizer is performed. If input signals are oversampled, then the quantization error could be reduced by modulating both the input and the output of the quantizer. The working principle is based on the fact that convolutions of bandpass signals would spread wider in the frequency spectrum than that of lowpass signals. Hence, by filtering the high frequency components, the signal-to-noise ratio (SNR) could be increased. Numerical simulation results show that the modulated quantization scheme could achieve an average of 13.0960dB to 21.4700dB improvements on SNR over the conventional scheme, depends on the types of bandlimited input signals.

Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521), 2004

In this paper a pure digital CMOS (90nm) dual band GSM low IF (1OOkHz) receiver section is presented. The incoming RF signal is first amplified using two differential LNAs (one for GSM and the other for DCS) and then down converted by two passive mixers to produce the low frequency I and Q signals. The 90 degrees phase shifted local oscillator signals are implemented on chip using two dividers by 4 and by 2 (working at 3.6GHz). The low IF strip will amplify and filter the I and Q signals. It has been built with digitally programmable gain stages including also a Buttemorth 2"d order polyphase active filter. The receiver has been designed to be compatible with a standard 10-bits ADC. The RX chain shows state-of-the-art NF performances (<2dB in GSM and <3dB in DCS) with an overall current consumption of 29mA at 1.4V supply (9mA for the.LNA, 17mA for the IF strip and 3mA for the divider by 2). The die area is 1.4mmx2.8mm. I.