Optimizing the energy-delay-ringing product in on-chip CMOS line drivers

To obtain higher performance with maximum devices and smaller chip size semiconductor devices are continuously shrinking. However, leakage power dissipation increases significantly with the technology scaling. Increasing demand for ultra low power devices has increased significantly since last decade and it compels advance technological solutions to fulfill power requirements of electronic appliances. As a result subthreshold operation region and different device optimization techniques attracts different researchers to achieve ultra low power design of VLSI circuits. Power supply reduction is supposed to be the main parameter to reduce power reduction. However, deep subthreshold region offers speed penalty degrading the overall performance of a device which suggests the need for optimizing device parameters. This paper analyzes the driver and interconnects performance by changing threshold voltage (V th ) and oxide thickness (T ox ) in subthreshold region. Further, it also compares the optimized driver performance and DTMOS driver performance at 0.4 V. Moreover, a large amount of gain in performance was observed when optimized interconnect is used with the optimized driver. Result shows that performance of a circuit enhances if the optimized driver is used compared to DTMOS driver.

IJEER, 2016

In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.

2004

Abstract This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing.

2002

Abstract In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay constraint is proposed. The energy formulations are obtained by using approximated expressions for the driving-point impedance of lossy coupled transmission lines which itself is derived by solving Telegrapher's equations.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-m TSMC CMOS technology and applied to a 4500-m long Metal4 bus. Circuit simulation results for different bus widths are presented.

IJEER, 2014

In this paper, an analysis of different delay lines based on CMOS architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

IEEE Journal of Solid-State Circuits, 1992

A CMOS off-chip signal driver with 2.5-3X smaller di/dt noise than the conventional design without incurring the penalty of signal delay is described. It minimizes L d i / d t effects by providing a controlled ramp rate for the output current. The circuit has a nearly constant output resistance for source ter-tion most suitable for the multichip packaging technology, ~~i~~ reduction obtained using these driver/receiver this work a 0. 2 5-w , 2.5-V CMOS technology was thosen [4]. The design, basic operation, and noise consid-by reducing the output signal swing by about a factor of 2 and circuitries may be in any In mination of transmission lines, and includes a receiver designed for the smaller signal swing. Simulations show a driverreceiver delay of 3 ns for a 7.5-cm line on a multichip package with a peak di/dt of only 12 mA/ns. Driver-receiver delay and noise measurements are also presented.

2010

International Journal of Circuit Theory and Applications, 2012

In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energyefficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of E i D j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing E i D j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results.