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Abstract
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The paper discusses RF power amplifiers, covering their operational frequency ranges and the various classes of amplifier topologies, including linear and nonlinear amplifications. It highlights the characteristics and applications of different amplifier classes (A, B, AB, C, D, E, F, and S) and emphasizes the importance of switching-mode amplifiers in achieving efficient signal amplification across a wide frequency spectrum.

Figures (492)
GER CAL CAL EEN h ot PE OS Wag CHEM Midge gs ds In practice, RF PAs are implemented as part of systems that include several sub- assemblies such as DC power supply unit for amplifier, line filter, housekeeping power supply, system controller, splitter, combiner, coupler, compensator, and PA modules, as illustrated in Figure 1.4. Several PA modules are combined to obtain higher power levels via combiners. Couplers are used to monitor the reflected and forward power and provide control signal to the system controller. The system controller then adjusts the level of RF input signal to deliver the desired amount of output power.
GER CAL CAL EEN h ot PE OS Wag CHEM Midge gs ds In practice, RF PAs are implemented as part of systems that include several sub- assemblies such as DC power supply unit for amplifier, line filter, housekeeping power supply, system controller, splitter, combiner, coupler, compensator, and PA modules, as illustrated in Figure 1.4. Several PA modules are combined to obtain higher power levels via combiners. Couplers are used to monitor the reflected and forward power and provide control signal to the system controller. The system controller then adjusts the level of RF input signal to deliver the desired amount of output power.
FIGURE 1.6 Measured gain variation vs. frequency for a switched-mode RF amplifier.
FIGURE 1.6 Measured gain variation vs. frequency for a switched-mode RF amplifier.
power delivered to the load = 31.9 dBm — 6 dBm = 25.9 dBm
power delivered to the load = 31.9 dBm — 6 dBm = 25.9 dBm
An RF signal, v,(t) = Bcost, is applied to a linear amplifier and then to a non- linear amplifier given in Figure 1.13 with output response v,(t) = a + a, Bcoswt + aB*cos*wt + 03$?coswt. Assuming that input and output impedances are equal to R, (a) calculate and plot the gain for the linear amplifier; and (b) obtain the second and third HD for the nonlinear amplifier when a) = 0, a, = 1, a = 3, a; = 1 and 6 = 1, B = 2. Calculate also the THD for both cases. Example
An RF signal, v,(t) = Bcost, is applied to a linear amplifier and then to a non- linear amplifier given in Figure 1.13 with output response v,(t) = a + a, Bcoswt + aB*cos*wt + 03$?coswt. Assuming that input and output impedances are equal to R, (a) calculate and plot the gain for the linear amplifier; and (b) obtain the second and third HD for the nonlinear amplifier when a) = 0, a, = 1, a = 3, a; = 1 and 6 = 1, B = 2. Calculate also the THD for both cases. Example
FIGURE 1.16 Simplified IMD measurement setup
FIGURE 1.16 Simplified IMD measurement setup
FIGURE 1.17 Illustration of the relation between the fundamental components and IM.
FIGURE 1.17 Illustration of the relation between the fundamental components and IM.
FIGURE 1.18 Second-order nonlinear amplifier output response, which has components at DC, f, and 2f.
FIGURE 1.18 Second-order nonlinear amplifier output response, which has components at DC, f, and 2f.
FIGURE 1.20 Nonlinear amplifier response, which has second- and third-order nonlinearities.
FIGURE 1.20 Nonlinear amplifier response, which has second- and third-order nonlinearities.
SURE 1.21 Equivalent circuit representation of linear amplifier mode of operation.
SURE 1.21 Equivalent circuit representation of linear amplifier mode of operation.
sph ISU 1.2. In our analysis, MOSFET is used as an active device. The ideal MOSFET transfer haracteristics are illustrated in Figure 1.24. There is a maximum drain current level or a corresponding gate-source voltage, Vs, that a MOSFET conducts. In the cutoff egion, the gate-source voltage, Vgg, is less than the threshold voltage or saturation oltage, V,,,, and the device is an open circuit or off. In the ohmic region, the device cts as a resistor with an almost constant on-resistance Rpg,,, and is equal to the ratio f drain voltage, Vps, and the drain current J). In the linear mode of operation, the levice operates in the active region where J, is a function of the gate-source voltage /gs and is defined by
sph ISU 1.2. In our analysis, MOSFET is used as an active device. The ideal MOSFET transfer haracteristics are illustrated in Figure 1.24. There is a maximum drain current level or a corresponding gate-source voltage, Vs, that a MOSFET conducts. In the cutoff egion, the gate-source voltage, Vgg, is less than the threshold voltage or saturation oltage, V,,,, and the device is an open circuit or off. In the ohmic region, the device cts as a resistor with an almost constant on-resistance Rpg,,, and is equal to the ratio f drain voltage, Vps, and the drain current J). In the linear mode of operation, the levice operates in the active region where J, is a function of the gate-source voltage /gs and is defined by
FIGURE 1.23 Load lines and bias points for linear amplifiers. Conduction Angles, Bias, and Quiescent Points for Linear Amplifiers
FIGURE 1.23 Load lines and bias points for linear amplifiers. Conduction Angles, Bias, and Quiescent Points for Linear Amplifiers
URE 1.25 J, vs. Vgs in the saturation region for the ideal NMOS device.
URE 1.25 J, vs. Vgs in the saturation region for the ideal NMOS device.
FIGURE 1.29 = Typical load line for class A amplifiers.
FIGURE 1.29 = Typical load line for class A amplifiers.
FIGURE 1.30 Typical drain-to-source voltage and drain current for class A amplifiers. Then, the efficiency from Equations 1.13, 1.98, and 1.99 i
FIGURE 1.30 Typical drain-to-source voltage and drain current for class A amplifiers. Then, the efficiency from Equations 1.13, 1.98, and 1.99 i
FIGURE 1.31 Typical load line for class B amplifiers.
FIGURE 1.31 Typical load line for class B amplifiers.
sURE 1.32 Typical drain-to-source voltage and drain current for class B amplifiers.
sURE 1.32 Typical drain-to-source voltage and drain current for class B amplifiers.
Class A, B, and AB amplifiers are considered to be linear amplifiers where the phase and amplitude of the output signal are linearly related to the amplitude and phase of the input signal. If efficiency is a more important parameter than linearity, then nonlinear amplifier classes such as class C, D, E, or F can be used. The conduction angle for class C amplifier is less than 180°, which makes this amplifier class have higher efficiencies than class B amplifiers. The typical drain-to-source voltage and drain current waveforms for class C amplifiers are illustrated in Figure 1.34. The drain efficiency for PA classes A, B, and C can also be calculated using the
Class A, B, and AB amplifiers are considered to be linear amplifiers where the phase and amplitude of the output signal are linearly related to the amplitude and phase of the input signal. If efficiency is a more important parameter than linearity, then nonlinear amplifier classes such as class C, D, E, or F can be used. The conduction angle for class C amplifier is less than 180°, which makes this amplifier class have higher efficiencies than class B amplifiers. The typical drain-to-source voltage and drain current waveforms for class C amplifiers are illustrated in Figure 1.34. The drain efficiency for PA classes A, B, and C can also be calculated using the
FIGURE 1.34 Typical drain-to-source voltage and drain current for class C amplifiers.
FIGURE 1.34 Typical drain-to-source voltage and drain current for class C amplifiers.
FIGURE 1.35 Efficiency distribution of conventional amplifiers. Class A, AB, and B amplifiers have been used for linear applications where ampli- tude modulation (AM), single-sideband modulation, and quadrate AM might be required. Classes C, D, E, and F are usually implemented for narrow band-tuned amplifiers when high efficiency is desired with high power. Classes A, B, AB, and C are operated as transconductance amplifiers, and the mode of operation depends on the conduction angle. In switch-mode amplifiers such as classes D, E, and F, the active device is intentionally driven into the saturation region, and it is operated as a switch rather than a current source unlike class A, AB, B, or C amplifiers, as shown in Figure 1.22. In theory, power dissipation in the transistor can be totally elimi- nated, and hence, 100% efficiency can be achieved for switching-mode amplifiers.
FIGURE 1.35 Efficiency distribution of conventional amplifiers. Class A, AB, and B amplifiers have been used for linear applications where ampli- tude modulation (AM), single-sideband modulation, and quadrate AM might be required. Classes C, D, E, and F are usually implemented for narrow band-tuned amplifiers when high efficiency is desired with high power. Classes A, B, AB, and C are operated as transconductance amplifiers, and the mode of operation depends on the conduction angle. In switch-mode amplifiers such as classes D, E, and F, the active device is intentionally driven into the saturation region, and it is operated as a switch rather than a current source unlike class A, AB, B, or C amplifiers, as shown in Figure 1.22. In theory, power dissipation in the transistor can be totally elimi- nated, and hence, 100% efficiency can be achieved for switching-mode amplifiers.
FIGURE 1.37 Complementary voltage switching class D amplifier.
FIGURE 1.37 Complementary voltage switching class D amplifier.
FIGURE 1.40 Voltage and current waveforms for basic class E amplifier.
FIGURE 1.40 Voltage and current waveforms for basic class E amplifier.
FIGURE 1.43 Class F amplifier with third harmonic peaking. voltage and current and wave shapes to minimize the overlap region between them to reduce the transistor power dissipation. This resu ciency and power capacity. In theory, an ideal class F ts in improvement of both effi- amplifier can control an infinite number of harmonics; it has a square voltage waveform and can give 100% effi- ciency. However, in practical applications, it is very d ifficult to control more than the fifth harmonics with class F amplifiers. The schematics of the basic class F amplifier with the third harmonic called class F, peaking and its voltage and current wave- forms are given in Figures 1.43 and 1.44, respective y. The class F amplifier shown
FIGURE 1.43 Class F amplifier with third harmonic peaking. voltage and current and wave shapes to minimize the overlap region between them to reduce the transistor power dissipation. This resu ciency and power capacity. In theory, an ideal class F ts in improvement of both effi- amplifier can control an infinite number of harmonics; it has a square voltage waveform and can give 100% effi- ciency. However, in practical applications, it is very d ifficult to control more than the fifth harmonics with class F amplifiers. The schematics of the basic class F amplifier with the third harmonic called class F, peaking and its voltage and current wave- forms are given in Figures 1.43 and 1.44, respective y. The class F amplifier shown
Summary of Basic Amplifier Performance Parameters
Summary of Basic Amplifier Performance Parameters
RF High-Power Transistor Material Properties
RF High-Power Transistor Material Properties
FIGURE 1.49 Rectifier circuit for voltage-controlled capacitor example.
FIGURE 1.49 Rectifier circuit for voltage-controlled capacitor example.
IGURE 1.50 Rectifier circuit simulation of voltage-controlled capacitor example.
IGURE 1.50 Rectifier circuit simulation of voltage-controlled capacitor example.
The large-signal model of a diode is shown in Figure 1.56 using PSpice. Example
The large-signal model of a diode is shown in Figure 1.56 using PSpice. Example
FIGURE 1.55 Output simulation response of an ideal switch.
FIGURE 1.55 Output simulation response of an ideal switch.
So when the diode is off, ie, V < Vy, then the diode capacitance can be approximated by
So when the diode is off, ie, V < Vy, then the diode capacitance can be approximated by
PROBLEMS
PROBLEMS
FIGURE 2.1 RF power transistor as a two-port network.
FIGURE 2.1 RF power transistor as a two-port network.
FIGURE 2.3.) FOM comparison of planar and trench MOSFET structures
FIGURE 2.3.) FOM comparison of planar and trench MOSFET structures
SURE 2.4 Trench MOSFETs: (a) current crowding in V-groove trench MOSFETs and (b) truncated V-groove.
SURE 2.4 Trench MOSFETs: (a) current crowding in V-groove trench MOSFETs and (b) truncated V-groove.
FIGURE 2.6 MOSFET structure capacitance illustration. oe ee In MOSFET structures, considerable capacitance is observed at the input due to the oxide layer. The simplest view of an n-channel MOSFET is shown in Figure 2.7, where the three capacitors, C,,, Cy, and C,,, represent the parasitic capacitances. These values can be manipulated to form the input capacitance, output capacitance, and transfer capacitance. C,, is the capacitance due to the overlap of the source and channel regions by the polysilicon gate. It is independent of the applied voltage. C,, consists of the part associated with the overlap of the polysilicon gate and the sili- con underneath the junction gate field effect transistor (JFET) region, which is also independent of the applied voltage and the capacitance associated with the depletion region immediately under the gate, which is a nonlinear function of the applied volt- age. This capacitance provides a feedback loop between the output and input circuit. C,, is also called the Miller capacitance because it causes the total dynamic input capacitance to become greater than the sum of the static capacitors. C,, is the capaci- tance associated with the body drift diode. It varies inversely with the square root
FIGURE 2.6 MOSFET structure capacitance illustration. oe ee In MOSFET structures, considerable capacitance is observed at the input due to the oxide layer. The simplest view of an n-channel MOSFET is shown in Figure 2.7, where the three capacitors, C,,, Cy, and C,,, represent the parasitic capacitances. These values can be manipulated to form the input capacitance, output capacitance, and transfer capacitance. C,, is the capacitance due to the overlap of the source and channel regions by the polysilicon gate. It is independent of the applied voltage. C,, consists of the part associated with the overlap of the polysilicon gate and the sili- con underneath the junction gate field effect transistor (JFET) region, which is also independent of the applied voltage and the capacitance associated with the depletion region immediately under the gate, which is a nonlinear function of the applied volt- age. This capacitance provides a feedback loop between the output and input circuit. C,, is also called the Miller capacitance because it causes the total dynamic input capacitance to become greater than the sum of the static capacitors. C,, is the capaci- tance associated with the body drift diode. It varies inversely with the square root
The input capacitance must be charged to the threshold voltage before the device begins to turn on and discharged to the plateau voltage before the device turns off. Therefore, the impedance of the drive circuitry and C,,, have a direct effect on the turn-on and turn-off delays. C,,, is made up of the drain-to-source capacitance, C,,, in parallel with the gate-to-drain capacitance, C,,, or
The input capacitance must be charged to the threshold voltage before the device begins to turn on and discharged to the plateau voltage before the device turns off. Therefore, the impedance of the drive circuitry and C,,, have a direct effect on the turn-on and turn-off delays. C,,, is made up of the drain-to-source capacitance, C,,, in parallel with the gate-to-drain capacitance, C,,, or
FIGURE 2.8 High-frequency, small-signal model for MOSFET transistor.
FIGURE 2.8 High-frequency, small-signal model for MOSFET transistor.
The nested sweep setup is When simulation is run, the I-V characteristics are obtained from the Probe interface. As seen from simulation results shown in Figure 2.12, V,,> V,,= 4.54 [V] as specified in the lib file that MOSFET conducts.
The nested sweep setup is When simulation is run, the I-V characteristics are obtained from the Probe interface. As seen from simulation results shown in Figure 2.12, V,,> V,,= 4.54 [V] as specified in the lib file that MOSFET conducts.
FIGURE 2.13 PSpice circuit to obtain C; iss for a given MOSFET.
FIGURE 2.13 PSpice circuit to obtain C; iss for a given MOSFET.
FIGURE 2.14 PSpice circuit to obtain C. Oss and C,,, (or C,,) for the given MOSFET.
FIGURE 2.14 PSpice circuit to obtain C. Oss and C,,, (or C,,) for the given MOSFET.
FIGURE 2.15 Nonlinear circuit representation of the given MOSFET.
FIGURE 2.15 Nonlinear circuit representation of the given MOSFET.
FIGURE 2.16 C-—V curves obtained using PSpice for the given MOSFET.
FIGURE 2.16 C-—V curves obtained using PSpice for the given MOSFET.
FIGURE 2.19 Simplified MOSFET equivalent circuit for switching analysis.
FIGURE 2.19 Simplified MOSFET equivalent circuit for switching analysis.
Equation 2.17 is used to determine the amount of time it takes to reach the gate- to-so time thres with urce threshold voltage, V,,,, to turn the device on. In our analysis, the following durations, f, to ¢,, in Figures 2.17 and 2.18 are derived by designating V,, as the hold voltage, V,,,, as the gate plateau voltage, V; as the voltage across MOSFET full current, and V,, as the drain-to-source voltage when the device is off. One important note is on the equation for ¢,. t, depends on the gate-to-source voltage, whic the p h changes with the applied voltage. rt, and t, can be accurately calculated with arameters given by the manufacturer data sheet. Hence, the drain-to-source voltage is
Equation 2.17 is used to determine the amount of time it takes to reach the gate- to-so time thres with urce threshold voltage, V,,,, to turn the device on. In our analysis, the following durations, f, to ¢,, in Figures 2.17 and 2.18 are derived by designating V,, as the hold voltage, V,,,, as the gate plateau voltage, V; as the voltage across MOSFET full current, and V,, as the drain-to-source voltage when the device is off. One important note is on the equation for ¢,. t, depends on the gate-to-source voltage, whic the p h changes with the applied voltage. rt, and t, can be accurately calculated with arameters given by the manufacturer data sheet. Hence, the drain-to-source voltage is
From Equations 2.37 and 2.38, we can find the drain-to-source voltage as
From Equations 2.37 and 2.38, we can find the drain-to-source voltage as
FIGURE 2.23 Power dissipation profile and the corresponding junction temperature.
FIGURE 2.23 Power dissipation profile and the corresponding junction temperature.
FIGURE 2.24 Transfer characteristics of MOSFETs vs. junction temperature, 7,.
FIGURE 2.24 Transfer characteristics of MOSFETs vs. junction temperature, 7,.
1S Over a certain value, is assumed. Safe operating area (SOA) is the region identified by the maximum value of the drain-to-source voltage and drain current that guarantees safe operation when the device is at the forward bias. The SOA for MOSFETs can be expressed by a constant- power line, which is limited by thermal resistance with pulse width as a parameter. MOSFETs can be safely operated over a very wide range within the breakdown voltage between the drain and the source without narrowing the high-voltage area because secondary breakdown does not occur in the high-voltage area. The typical SOA for a MOSFET is illustrated in Figure 2.25. The relationship between SOA and device parameters such as Ry, and Pamax 1S given in Figure 2.26. In Figure 2.26, the actual response of device dissipation characteristics, which has steeper slope when it is over a certain value, is assumed. dson
1S Over a certain value, is assumed. Safe operating area (SOA) is the region identified by the maximum value of the drain-to-source voltage and drain current that guarantees safe operation when the device is at the forward bias. The SOA for MOSFETs can be expressed by a constant- power line, which is limited by thermal resistance with pulse width as a parameter. MOSFETs can be safely operated over a very wide range within the breakdown voltage between the drain and the source without narrowing the high-voltage area because secondary breakdown does not occur in the high-voltage area. The typical SOA for a MOSFET is illustrated in Figure 2.25. The relationship between SOA and device parameters such as Ry, and Pamax 1S given in Figure 2.26. In Figure 2.26, the actual response of device dissipation characteristics, which has steeper slope when it is over a certain value, is assumed. dson
2.8 MOSFET GATE THRESHOLD AND PLATEAU VOLTAGE MOSFET gate threshold, V,,, and Miller p ateau voltage, V, ep Values are required to calculate the switching times for MOSFETs given in Section 2.3. However, these values are not well defined in the manufacturer data sheet. As a result, they need to be obtained using the measured transfer c voltage, V, ap 1S determined by finding haracteristics of MOSFETs. The plateau two different values of drain current at the same temperature to identify the gate-to-source voltages, V,, for the given load cur- rent, J,. The drain current when the M Chapter 1 and found from OSFET is in the active region was given in
2.8 MOSFET GATE THRESHOLD AND PLATEAU VOLTAGE MOSFET gate threshold, V,,, and Miller p ateau voltage, V, ep Values are required to calculate the switching times for MOSFETs given in Section 2.3. However, these values are not well defined in the manufacturer data sheet. As a result, they need to be obtained using the measured transfer c voltage, V, ap 1S determined by finding haracteristics of MOSFETs. The plateau two different values of drain current at the same temperature to identify the gate-to-source voltages, V,, for the given load cur- rent, J,. The drain current when the M Chapter 1 and found from OSFET is in the active region was given in
The constant K is found from Equation 2.74 as Using Equation 2.72, the threshold voltage, V,,, is calculated as
The constant K is found from Equation 2.74 as Using Equation 2.72, the threshold voltage, V,,, is calculated as
Example Obtain the h-parameter of the circuit shown in Figure 3.3 if L, =1,=M=1H.
Example Obtain the h-parameter of the circuit shown in Figure 3.3 if L, =1,=M=1H.
From KVL on the secondary side,
From KVL on the secondary side,
FIGURE 3.4 Conversion of transformer coupling circuit to equivalent circuit.
FIGURE 3.4 Conversion of transformer coupling circuit to equivalent circuit.
Example The ABCD parameter of network 2, N,, is
Example The ABCD parameter of network 2, N,, is
where A = 1. The same result is obtained.
where A = 1. The same result is obtained.
So, the Y-matrix for the 7-network is then
So, the Y-matrix for the 7-network is then
The hybrid matrix for the 7-network can now be constructed as Parameters h,, and h,, are obtained when port 1 is open circuited as
The hybrid matrix for the 7-network can now be constructed as Parameters h,, and h,, are obtained when port 1 is open circuited as
Parameters B and D are determined when port 2 is short circuited as
Parameters B and D are determined when port 2 is short circuited as
IRE 3.7 Series connection of two-port networks.
IRE 3.7 Series connection of two-port networks.
FIGURE 3.8 Parallel connection of two-port networks.
FIGURE 3.8 Parallel connection of two-port networks.
where A is for the determinant of the corresponding matrix. At this point, it is now clearer that networks 1, Y, and 4 are cascaded. We need to determine the ABCD matrix of each network in this connection, as shown in Figure 3.13. The first step is then to convert the admittance matrix in Equation 3.54 to an ABCD parameter using the conversion table. The conversion table gives the relation as FIGURE 3.13 Cascade connection of the final circuit.
where A is for the determinant of the corresponding matrix. At this point, it is now clearer that networks 1, Y, and 4 are cascaded. We need to determine the ABCD matrix of each network in this connection, as shown in Figure 3.13. The first step is then to convert the admittance matrix in Equation 3.54 to an ABCD parameter using the conversion table. The conversion table gives the relation as FIGURE 3.13 Cascade connection of the final circuit.
The ABCD matrices for networks 1 and 4 are obtained as MATLAB® Script for Network Analysis of RF Amplifier
The ABCD matrices for networks 1 and 4 are obtained as MATLAB® Script for Network Analysis of RF Amplifier
Example
Example
FIGURE 3.17 Small-signal MOSFET model.
FIGURE 3.17 Small-signal MOSFET model.
FIGURE 3.18 The simplified equivalent circuit for the MOSFET small-signal model. The small-signal MOSFET model circuit given in Figure 3.17 can be ana- lyzed when each of the components is represented as a network with the con- nection that they are introduced in the circuit, as shown in Figure 3.19. From Figure 3.19, it is seen that network 2, Nj, and network 3, N;, are connected in parallel. The overall parallel-connected network, N>3, can be found from nection that they are introduced in the circuit, as shown in Figure 3.19. From
FIGURE 3.18 The simplified equivalent circuit for the MOSFET small-signal model. The small-signal MOSFET model circuit given in Figure 3.17 can be ana- lyzed when each of the components is represented as a network with the con- nection that they are introduced in the circuit, as shown in Figure 3.19. From Figure 3.19, it is seen that network 2, Nj, and network 3, N;, are connected in parallel. The overall parallel-connected network, N>3, can be found from nection that they are introduced in the circuit, as shown in Figure 3.19. From
FIGURE 3.19 The network equivalent circuit for the MOSFET small-signal model.
FIGURE 3.19 The network equivalent circuit for the MOSFET small-signal model.
FIGURE 3.22 One-port network for scattering parameter analysis.
FIGURE 3.22 One-port network for scattering parameter analysis.
Consider a transistor network that is represented as a two-port network and con- nected between the source and the load. It is assumed that the generator or source and load impedances are equal and given to be R,. The transistor is represented by the following Z parameters, as shown in Figure 3.24. Find the current scattering matrix, S!.
Consider a transistor network that is represented as a two-port network and con- nected between the source and the load. It is assumed that the generator or source and load impedances are equal and given to be R,. The transistor is represented by the following Z parameters, as shown in Figure 3.24. Find the current scattering matrix, S!.
Hence, the inverse of the matrix from Equations 3.97 through 3.99 is equal to
Hence, the inverse of the matrix from Equations 3.97 through 3.99 is equal to
Substituting Equation 3.86 into Equations 3.103 and 3.104 gives
Substituting Equation 3.86 into Equations 3.103 and 3.104 gives
The S-matrix in Equation 3.109 is called a normalized scattering matrix. It can be proven that
The S-matrix in Equation 3.109 is called a normalized scattering matrix. It can be proven that
From Equation 3.167, it is seen that the maximum power transfer occurs when
From Equation 3.167, it is seen that the maximum power transfer occurs when
Since from Equations 3.168 and 3.169,
Since from Equations 3.168 and 3.169,
SURE 3.30 Network analyzer direct measurement setup for transistors.
SURE 3.30 Network analyzer direct measurement setup for transistors.
FIGURE 3.33 GCPW for SOLT calibration fixture implementation.
FIGURE 3.33 GCPW for SOLT calibration fixture implementation.
MATLAB Model Calculations MATLAB CPW Calculations
MATLAB Model Calculations MATLAB CPW Calculations
Ansoft Designer TRL Calculations 3.5.3.1.2 Quarter-Wave Stub Design
Ansoft Designer TRL Calculations 3.5.3.1.2 Quarter-Wave Stub Design
The SOLT test fixtures are designed repeating the method described above; they are implemented as shown in Figures 3.34 through 3.37. Rogers 4003 with relative permittivity of 3.38 is used as a dielectric substrate. The board material has substrate thickness of 0.060 in. with 1-oz. copper plating on both sides. The gap size of 10 mils is used as discussed and illustrated in Figure 3.33. In addition, several biases were
The SOLT test fixtures are designed repeating the method described above; they are implemented as shown in Figures 3.34 through 3.37. Rogers 4003 with relative permittivity of 3.38 is used as a dielectric substrate. The board material has substrate thickness of 0.060 in. with 1-oz. copper plating on both sides. The gap size of 10 mils is used as discussed and illustrated in Figure 3.33. In addition, several biases were
FIGURE 3.36 “Load” calibration test fixture. placed through the board in order to provide a good electrical connection between the top and bottom layer ground planes to further improve the grounding of the fixture. Each board layout for the various fixtures incorporated a 0.25-in. section of transmission line at the output of each connector. This consistent length of transmis- sion line is important in order to ensure that the ports of the network analyzer are subjected to the same additional line impedance regardless of the fixture connected. By doing so, the error matrix generated by the analyzer will be appropriate for this
FIGURE 3.36 “Load” calibration test fixture. placed through the board in order to provide a good electrical connection between the top and bottom layer ground planes to further improve the grounding of the fixture. Each board layout for the various fixtures incorporated a 0.25-in. section of transmission line at the output of each connector. This consistent length of transmis- sion line is important in order to ensure that the ports of the network analyzer are subjected to the same additional line impedance regardless of the fixture connected. By doing so, the error matrix generated by the analyzer will be appropriate for this
FIGURE 3.38 BFR92 bias simulation test setup. selected length. 1wo subminiature version A (ovisAA) Connectors were mounted On ports 1 and 2 of each fixture, which were utilized for connecting to the network analyzer. Once the network analyzer had been calibrated by means of a two-port calibra- tion using the SOLT method with the designed calibration standards, as shown in Figures 3.34 and 3.37, the biasing circuit depicted in Figure 3.38 is simulated with the nonlinear circuit simulator of Ansoft Designer and implemented to characterize the active device, BFR92, for various biasing conditions. Simulation of the biasing circuit is needed to determine the best DC biasing conditions. DC bias conditions can be determined by adjusting the voltage sources V,,,. and Vioiecior While main- taining constant current limiting resistors R,,. ANd Rooector: A 425-nH inductor was placed in series with each current limiting resistor with their respective transistor pins in order to isolate these ports from the DC biases at microwave frequencies. The inductor selected (PN: CC21T36K2406S) is a conical inductor whose resonance frequency was greater than 1 GHz. In addition, a 0.033-pF capacitor was added in order to form a low-pass filter with the current limiting resistors. The sole purpose of this RC was to provide a clean DC supply at the base and collector of the transis- tor under test. Utilizing the test setup shown in Figure 3.39, the BFR92 transistor ase
FIGURE 3.38 BFR92 bias simulation test setup. selected length. 1wo subminiature version A (ovisAA) Connectors were mounted On ports 1 and 2 of each fixture, which were utilized for connecting to the network analyzer. Once the network analyzer had been calibrated by means of a two-port calibra- tion using the SOLT method with the designed calibration standards, as shown in Figures 3.34 and 3.37, the biasing circuit depicted in Figure 3.38 is simulated with the nonlinear circuit simulator of Ansoft Designer and implemented to characterize the active device, BFR92, for various biasing conditions. Simulation of the biasing circuit is needed to determine the best DC biasing conditions. DC bias conditions can be determined by adjusting the voltage sources V,,,. and Vioiecior While main- taining constant current limiting resistors R,,. ANd Rooector: A 425-nH inductor was placed in series with each current limiting resistor with their respective transistor pins in order to isolate these ports from the DC biases at microwave frequencies. The inductor selected (PN: CC21T36K2406S) is a conical inductor whose resonance frequency was greater than 1 GHz. In addition, a 0.033-pF capacitor was added in order to form a low-pass filter with the current limiting resistors. The sole purpose of this RC was to provide a clean DC supply at the base and collector of the transis- tor under test. Utilizing the test setup shown in Figure 3.39, the BFR92 transistor ase
FIGURE 3.41 Quarter-wave CPW transmission line used for simulations.
FIGURE 3.41 Quarter-wave CPW transmission line used for simulations.
FIGURE 3.42 Quarter-wave short-circuit simulation.
FIGURE 3.42 Quarter-wave short-circuit simulation.
n Ansoft Designer. Before attaching the stubs, the S parameters of the CPW trans nission line were captured to serve as a reference when comparing the results witl he stubs attached. Figure 3.44 provides the plot of the S parameters with no stub: ttached. It is shown in Figure 3.35 that S,, = S,, and S,, = S,,. This is consisten vith what would be expected. There should be no forward (S,,) or reverse gain (S;, nd very little reflection at both ends (S,, and S,,) due to the 50 Q transmission line vhich provides a A good impedance match to the ports. ed ~~ ace — a e ?- wx “ca: 4 se ¢ or
n Ansoft Designer. Before attaching the stubs, the S parameters of the CPW trans nission line were captured to serve as a reference when comparing the results witl he stubs attached. Figure 3.44 provides the plot of the S parameters with no stub: ttached. It is shown in Figure 3.35 that S,, = S,, and S,, = S,,. This is consisten vith what would be expected. There should be no forward (S,,) or reverse gain (S;, nd very little reflection at both ends (S,, and S,,) due to the 50 Q transmission line vhich provides a A good impedance match to the ports. ed ~~ ace — a e ?- wx “ca: 4 se ¢ or
FIGURE 3.46 Quarter-wave short-circuit stub attached at input port.
FIGURE 3.46 Quarter-wave short-circuit stub attached at input port.
JRE 3.48 Quarter-wave stub attached to both input and output ports.
JRE 3.48 Quarter-wave stub attached to both input and output ports.
column titled “B” in Table 3.6. The measured S$ parameters were then plotted wit the vendor-supplied spice model under the same biasing conditions, as well as th catalog vendor data for the given biases. These results are detailed in Figures 3.5 through 3.54 when V., = 1O[V] and J, = 5[{mA]. As detailed in the S parameter plots the data measured using the BFR92 test fixture aligned themselves closely with bot the vendor-supplied spice model and the vendor catalog data. The comparison of th measured and simulated data has also been done for all other conditions shown i Table 3.6. The agreement again was seen on all of them.
column titled “B” in Table 3.6. The measured S$ parameters were then plotted wit the vendor-supplied spice model under the same biasing conditions, as well as th catalog vendor data for the given biases. These results are detailed in Figures 3.5 through 3.54 when V., = 1O[V] and J, = 5[{mA]. As detailed in the S parameter plots the data measured using the BFR92 test fixture aligned themselves closely with bot the vendor-supplied spice model and the vendor catalog data. The comparison of th measured and simulated data has also been done for all other conditions shown i Table 3.6. The agreement again was seen on all of them.
IGURE 3.50 Quarter-wave stub with capacitor attached at both input and output ports.
IGURE 3.50 Quarter-wave stub with capacitor attached at both input and output ports.
FIGURE 3.51 Input return loss comparison (S,,); Vog = 10 V, J; =5 mA.
FIGURE 3.51 Input return loss comparison (S,,); Vog = 10 V, J; =5 mA.
FIGURE 3.54 Forward gain comparison (S},); Voz = 10 V, J. =5 mA. FIGURE 3.53 Reverse isolation comparison (S,,); Vo; = 10 V, J, =5 mA.
FIGURE 3.54 Forward gain comparison (S},); Voz = 10 V, J. =5 mA. FIGURE 3.53 Reverse isolation comparison (S,,); Vo; = 10 V, J, =5 mA.
FIGURE 3.56 Transistor amplifier representation as a two-port network.
FIGURE 3.56 Transistor amplifier representation as a two-port network.
FIGURE 3.57 Transistor scattering parameter representation.
FIGURE 3.57 Transistor scattering parameter representation.
FIGURE 3.60 Parallel network connection of transistor with shunt feedback network. FIGURE 3.60 Parallel network connection of transistor with shunt feedback network.
FIGURE 3.60 Parallel network connection of transistor with shunt feedback network. FIGURE 3.60 Parallel network connection of transistor with shunt feedback network.
FIGURE 3.61 Network connection with source impedance.
FIGURE 3.61 Network connection with source impedance.
RE 3.64 Transistor amplifier with all the networks including matching networks.
RE 3.64 Transistor amplifier with all the networks including matching networks.
FIGURE 3.68 MOSFET package parasitics with intrinsic parameters.
FIGURE 3.68 MOSFET package parasitics with intrinsic parameters.
Using Equations 3.257 through 3.260, Z' parameters can be obtained as In practice, the device parasitics are measured using a test fixture that interfaces the device with the equipment. The DUT can be characterized accurately by remov- ing the test fixture characteristics from the measured results. VNA is commonly used as the measurement equipment to characterize the RF and microwave compo- nents. To characterize the device parasitics, the § parameters for the DUT must first be de-embedded from the total measured S parameters. The input and output sides of the test fixture also have some reactance caused by the coaxial-to-CPW transition.
Using Equations 3.257 through 3.260, Z' parameters can be obtained as In practice, the device parasitics are measured using a test fixture that interfaces the device with the equipment. The DUT can be characterized accurately by remov- ing the test fixture characteristics from the measured results. VNA is commonly used as the measurement equipment to characterize the RF and microwave compo- nents. To characterize the device parasitics, the § parameters for the DUT must first be de-embedded from the total measured S parameters. The input and output sides of the test fixture also have some reactance caused by the coaxial-to-CPW transition.
FIGURE 3.71 S parameter plot using extracted values of TO-247 MOSFET.
FIGURE 3.71 S parameter plot using extracted values of TO-247 MOSFET.
FIGURE 3.73 Simulation of S parameter plot using exact values of TO-247 MOSFET.
FIGURE 3.73 Simulation of S parameter plot using exact values of TO-247 MOSFET.
FIGURE 3.76 Effect of test fixture in DUT measurement.
FIGURE 3.76 Effect of test fixture in DUT measurement.
If the forward error model shown in Figure 3.78 was modified to include the test fixture before and after the DUT, it would look like the signal flow graph shown in Figure 3.79. This diagram shows the original calibration terms being cascaded with the S parameters from the test fixture.
If the forward error model shown in Figure 3.78 was modified to include the test fixture before and after the DUT, it would look like the signal flow graph shown in Figure 3.79. This diagram shows the original calibration terms being cascaded with the S parameters from the test fixture.
FIGURE 3.79 Forward model for six-error term with test fixture.
FIGURE 3.79 Forward model for six-error term with test fixture.
FIGURE 3.80 Modified forward model for six-error term with test fixture.
FIGURE 3.80 Modified forward model for six-error term with test fixture.
FIGURE 3.81 TO-247 MOSFET package measurement setup.
FIGURE 3.81 TO-247 MOSFET package measurement setup.
FIGURE 3.83 Simulated TO-247 MOSFET zero bias equivalent circuit with test fixture.
FIGURE 3.83 Simulated TO-247 MOSFET zero bias equivalent circuit with test fixture.
-IGURE 3.88 Small-signal model of an amplifier.
-IGURE 3.88 Small-signal model of an amplifier.
FIGURE 4.1 Ideal resonant network response. vhere A is constant, and s = j@. Substitution of Equation 4.3 into Equation 4.2 gives
FIGURE 4.1 Ideal resonant network response. vhere A is constant, and s = j@. Substitution of Equation 4.3 into Equation 4.2 gives
Equation 4.5 is called the characteristic equation. The roots of the equation are
Equation 4.5 is called the characteristic equation. The roots of the equation are
In terms of the quality factor, the roots given by Equations 4.6 and 4.7 can be expressed as Natural response of an underdamped parallel RLC circuit
In terms of the quality factor, the roots given by Equations 4.6 and 4.7 can be expressed as Natural response of an underdamped parallel RLC circuit
Natural response of an overdamped parallel RLC circuit Introduction to RF Power Amplifier Design and Simulation
Natural response of an overdamped parallel RLC circuit Introduction to RF Power Amplifier Design and Simulation
FIGURE 4.5 Pole-zero diagram for complex conjugate roots.
FIGURE 4.5 Pole-zero diagram for complex conjugate roots.
then the resonance element values are
then the resonance element values are
Equations 4.38 and 4.39 are identical to the ones obtained for a parallel resonant -ircuit. The damping characteristics of the series resonant network follow the condi- ions listed in Equation 4.13. The time domain representation of a series resonant 1etwork current response illustrating underdamped and overdamped cases is illus- rated in Figures 4.9 and 4.10, respectively. L and C values are taken to be 100 mH ind 10 wF for an underdamped case, whereas for an overdamped case, L and C values are taken to be 200 mH and 10 pF. R values are varied to see their effect on current response for damping.
Equations 4.38 and 4.39 are identical to the ones obtained for a parallel resonant -ircuit. The damping characteristics of the series resonant network follow the condi- ions listed in Equation 4.13. The time domain representation of a series resonant 1etwork current response illustrating underdamped and overdamped cases is illus- rated in Figures 4.9 and 4.10, respectively. L and C values are taken to be 100 mH ind 10 wF for an underdamped case, whereas for an overdamped case, L and C values are taken to be 200 mH and 10 pF. R values are varied to see their effect on current response for damping.
FIGURE 4.10 Series resonant network response for an overdamped case.
FIGURE 4.10 Series resonant network response for an overdamped case.
The phase of the transfer function is found from
The phase of the transfer function is found from
FIGURE 4.12 Series resonant circuit transfer function characteristics.
FIGURE 4.12 Series resonant circuit transfer function characteristics.
URE 4.13 High-frequency representation of (a) an inductor and (b) a capacitor.
URE 4.13 High-frequency representation of (a) an inductor and (b) a capacitor.
The impedance given in Equation 4.55 can be converted to admittance as
The impedance given in Equation 4.55 can be converted to admittance as
FIGURE 4.16 MATLAB GUI window for air core inductor design.
FIGURE 4.16 MATLAB GUI window for air core inductor design.
FIGURE 4.17, MATLAB GUI plots for resonance and quality factor.
FIGURE 4.17, MATLAB GUI plots for resonance and quality factor.
FIGURE 4.18 LC resonant network with ideal components and source.
FIGURE 4.18 LC resonant network with ideal components and source.
The quality factor of the circuit is found from its equivalent impedance as The frequency characteristics of the circuit are plotted in Figure 4.19 when L = 0.5 pH C = 2500 pF, and R = 50 Q. The quality factor of the circuit is found from its equivalent impedance as FIGURE 4.19 The frequency characteristics of LC network with source.
The quality factor of the circuit is found from its equivalent impedance as The frequency characteristics of the circuit are plotted in Figure 4.19 when L = 0.5 pH C = 2500 pF, and R = 50 Q. The quality factor of the circuit is found from its equivalent impedance as FIGURE 4.19 The frequency characteristics of LC network with source.
FIGURE 4.20 Addition of loss to parallel LC network. The resonant frequency of the network is now equal to
FIGURE 4.20 Addition of loss to parallel LC network. The resonant frequency of the network is now equal to
FIGURE 4.21 Attenuation profile of LC network with loss resistor. Ene a Ce EE Ree ee oe Ree Nel Nh he het ae ee When the reactive components are lossy, they impact the Q factor of the overall circuit. For instance, consider the resonant circuit with source resistance in Figure 4.18. The quality factor of the circuit vs. various source resistance values when L = 0.5 pH and C = 2500 pF have been illustrated in Figure 4.23. For the same frequency, the quality factor increases as the value of source resistance, R,, increases. As a
FIGURE 4.21 Attenuation profile of LC network with loss resistor. Ene a Ce EE Ree ee oe Ree Nel Nh he het ae ee When the reactive components are lossy, they impact the Q factor of the overall circuit. For instance, consider the resonant circuit with source resistance in Figure 4.18. The quality factor of the circuit vs. various source resistance values when L = 0.5 pH and C = 2500 pF have been illustrated in Figure 4.23. For the same frequency, the quality factor increases as the value of source resistance, R,, increases. As a
FIGURE 4.23 Quality factor of LC network for different source resistance values.
FIGURE 4.23 Quality factor of LC network for different source resistance values.
IGURE 4.24 Attenuation profile of LC network for different source resistance values.
IGURE 4.24 Attenuation profile of LC network for different source resistance values.
FIGURE 4.26 Equivalent loaded LC resonant circuit at resonance.
FIGURE 4.26 Equivalent loaded LC resonant circuit at resonance.
This can be accomplished by equating the real and imaginary parts as
This can be accomplished by equating the real and imaginary parts as
*. The load voltage with the resonant circuit is found from Introduction to RF Power Amplifier Design and Simulation The insertion loss is then found from
*. The load voltage with the resonant circuit is found from Introduction to RF Power Amplifier Design and Simulation The insertion loss is then found from
FIGURE 4.29 Attenuation profile for a parallel resonant network.
FIGURE 4.29 Attenuation profile for a parallel resonant network.
SURE 4.32 (a) Series loss added for capacitor and (b) equivalent parallel network.
SURE 4.32 (a) Series loss added for capacitor and (b) equivalent parallel network.
FIGURE 4.33 Inductively coupled resonators.
FIGURE 4.33 Inductively coupled resonators.
The value of the capacitor used to couple two identical resonant circuits is found
The value of the capacitor used to couple two identical resonant circuits is found
FIGURE 4.40 Attenuation profile for inductively coupled resonators.
FIGURE 4.40 Attenuation profile for inductively coupled resonators.
FIGURE 4.41 LC impedance transformer for inductive load.
FIGURE 4.41 LC impedance transformer for inductive load.
FIGURE 4.42 LC impedance transformer for capacitive load.
FIGURE 4.42 LC impedance transformer for capacitive load.
Solution
Solution
When the program is executed, the following calculated values are displayed via MATLAB Command Window.
When the program is executed, the following calculated values are displayed via MATLAB Command Window.
FIGURE 4.45 Implementation of unbalanced LC network.
FIGURE 4.45 Implementation of unbalanced LC network.
FIGURE 4.49 Capacitive voltage divider with parallel-to-series transformation.
FIGURE 4.49 Capacitive voltage divider with parallel-to-series transformation.
FIGURE 4.53 Attenuation profile for parallel resonant circuit with tapped-C.
FIGURE 4.53 Attenuation profile for parallel resonant circuit with tapped-C.
FIGURE 4.54 (a) Tapped-L impedance transformer. (b) Tapped-L impedance transformer with parallel-to-series transformation.
FIGURE 4.54 (a) Tapped-L impedance transformer. (b) Tapped-L impedance transformer with parallel-to-series transformation.
From the given information for the transistor,
From the given information for the transistor,
FIGURE 4.58 Output network transformation for tapped-L transformer.
FIGURE 4.58 Output network transformation for tapped-L transformer.
Consider the capacitively coupled amplifier circuit shown in Figure 4.60. Design the resonator-tuned amplifier circuit at a resonant frequency of 100 MHz, 3-dB bandwidth of 5 MHz, and source and load impedances of 50 and 12 Q, respec- tively. Assume that the inductor Qs are 65 at the frequency of interest. Integrate a tapped-C transformer to your circuit to match load impedance to source
Consider the capacitively coupled amplifier circuit shown in Figure 4.60. Design the resonator-tuned amplifier circuit at a resonant frequency of 100 MHz, 3-dB bandwidth of 5 MHz, and source and load impedances of 50 and 12 Q, respec- tively. Assume that the inductor Qs are 65 at the frequency of interest. Integrate a tapped-C transformer to your circuit to match load impedance to source
FIGURE 4.60 Capacitively coupled amplifier circuit. impedance. (a) Calculate resonator and tapped-C component values. (b) Now, using the results you obtained, develop a generic MATLAB program to design a capacitively coupled circuit with a tapped-C transformer to match the input and output impedances. Your program should take the input values as source imped- ance, load impedance, center frequency, 3-dB bandwidth, and inductor quality factor, and calculate and illustrate the resonator and tapped-C component values. Test the accuracy of your program using the values in part (a).
FIGURE 4.60 Capacitively coupled amplifier circuit. impedance. (a) Calculate resonator and tapped-C component values. (b) Now, using the results you obtained, develop a generic MATLAB program to design a capacitively coupled circuit with a tapped-C transformer to match the input and output impedances. Your program should take the input values as source imped- ance, load impedance, center frequency, 3-dB bandwidth, and inductor quality factor, and calculate and illustrate the resonator and tapped-C component values. Test the accuracy of your program using the values in part (a).
FIGURE 4.65 Resonator networks coupling. (a) Capacitively coupled resonator network and (b) inductively coupled resonator network.
FIGURE 4.65 Resonator networks coupling. (a) Capacitively coupled resonator network and (b) inductively coupled resonator network.
FIGURE 5.1. Matching network implementation for RF power amplifiers.
FIGURE 5.1. Matching network implementation for RF power amplifiers.
Dividing Equations 5.1 and 5.2 by Az and assuming that Az > 0, we obtain
Dividing Equations 5.1 and 5.2 by Az and assuming that Az > 0, we obtain
FIGURE 5.4 Input impedance calculation on the transmission line.
FIGURE 5.4 Input impedance calculation on the transmission line.
FIGURE 5.9 Impedance variation for a short-circuited transmission line.
FIGURE 5.9 Impedance variation for a short-circuited transmission line.
IGURE 5.8 Short-circuited transmission line.
IGURE 5.8 Short-circuited transmission line.
The location of the first circle that is always inside the unit circle in the complex reflection coefficient plane with the corresponding radius is
The location of the first circle that is always inside the unit circle in the complex reflection coefficient plane with the corresponding radius is
FIGURE 5.15 Conformal mapping of constant resistances.
FIGURE 5.15 Conformal mapping of constant resistances.
FIGURE 5.16 Conformal mapping of constant reactances.
FIGURE 5.16 Conformal mapping of constant reactances.
are plotted together, we obtain the ZY chart, as shown in Figure 5.21. That means a 180° phase shift for the reflection coefficient gives the value of admittance for the corresponding impedance value. When an impedance point is marked on the Smith chart, moving 180° in the clockwise direction gives the value admittance. Instead of repeating this for each impedance point on the Smith chart, we can keep the location of the impedance fixed and rotate the Smith chart by 180°. This gives the admittance chart as shown in Figure 5.20. When both Z and Y charts are plotted together, we obtain the ZY chart, as shown in Figure 5.21.
are plotted together, we obtain the ZY chart, as shown in Figure 5.21. That means a 180° phase shift for the reflection coefficient gives the value of admittance for the corresponding impedance value. When an impedance point is marked on the Smith chart, moving 180° in the clockwise direction gives the value admittance. Instead of repeating this for each impedance point on the Smith chart, we can keep the location of the impedance fixed and rotate the Smith chart by 180°. This gives the admittance chart as shown in Figure 5.20. When both Z and Y charts are plotted together, we obtain the ZY chart, as shown in Figure 5.21.
The normalized reactance value of the inductor is equal to
The normalized reactance value of the inductor is equal to
FIGURE 5.25 Matching network between load and transmission line.
FIGURE 5.25 Matching network between load and transmission line.
FIGURE 5.26 Eight possible L-matching network sections.
FIGURE 5.26 Eight possible L-matching network sections.
From Equation 5.95, there exist two possible solutions for B and consequently X. Both of these solutions are physically realizable and constitute all the values of B and X. The positive value of X gives an inductor; the negative value of X gives a capacitor. Similarly, the positive value of B gives a capacitor, and the negative value of B gives an inductor. In either of the configurations of Figure 5.27, the reactive elements may be either nductors or capacitors. As a result, there are eight distinct possibilities, as shown n Figure 5.26, for the matching circuit for various load impedances. If the nor- nalized load impedance, z, = Z,/Zo, is inside the 1 + jx circle on the Smith chart, hen the circuit of Figure 5.27a should be used. If the normalized load impedance s outside the | + jx circle on the Smith chart, the circuit of Figure 5.27b should e used. The | + jx circle is the resistance circle on the impedance Smith chart for vhich r= 1.
From Equation 5.95, there exist two possible solutions for B and consequently X. Both of these solutions are physically realizable and constitute all the values of B and X. The positive value of X gives an inductor; the negative value of X gives a capacitor. Similarly, the positive value of B gives a capacitor, and the negative value of B gives an inductor. In either of the configurations of Figure 5.27, the reactive elements may be either nductors or capacitors. As a result, there are eight distinct possibilities, as shown n Figure 5.26, for the matching circuit for various load impedances. If the nor- nalized load impedance, z, = Z,/Zo, is inside the 1 + jx circle on the Smith chart, hen the circuit of Figure 5.27a should be used. If the normalized load impedance s outside the | + jx circle on the Smith chart, the circuit of Figure 5.27b should e used. The | + jx circle is the resistance circle on the impedance Smith chart for vhich r= 1.
The admittance is then wired from Equation 5.102 as
The admittance is then wired from Equation 5.102 as
G,,=Y,, then tan Bd = —B,/2Y). As a result, we have solutions for d a
G,,=Y,, then tan Bd = —B,/2Y). As a result, we have solutions for d a
FIGURE 5.29 Matching networks between the load and transmission line.
FIGURE 5.29 Matching networks between the load and transmission line.
FIGURE 5.30 Generic two L-matching networks between source and load impedances. Separate real and imaginary parts,
FIGURE 5.30 Generic two L-matching networks between source and load impedances. Separate real and imaginary parts,
As can be seen, the analytical calculation of the impedance transformation and matching is tedious. Instead, we can apply the Smith chart to the same task. For this, there is a standard procedure that needs to be followed. The design procedure for matching source impedance to a load impedance using the Smith chart can be outlined as follows:
As can be seen, the analytical calculation of the impedance transformation and matching is tedious. Instead, we can apply the Smith chart to the same task. For this, there is a standard procedure that needs to be followed. The design procedure for matching source impedance to a load impedance using the Smith chart can be outlined as follows:
FIGURE 5.32 Possible L-matching networks to match source and load impedance.
FIGURE 5.32 Possible L-matching networks to match source and load impedance.
FIGURE 5.36 Representation of dependent node.
FIGURE 5.36 Representation of dependent node.
Hence, we obtain
Hence, we obtain
FIGURE 5.45 Input impedance using ZY Smith chart.
FIGURE 5.45 Input impedance using ZY Smith chart.
As aresult, the scattering matrix for symmetrical, lossless directional coupler car be obtained as
As aresult, the scattering matrix for symmetrical, lossless directional coupler car be obtained as
FIGURE 6.3 Symmetrical two-line microstrip directional coupler.
FIGURE 6.3 Symmetrical two-line microstrip directional coupler.
The physical length of the directional coupler is obtained using
The physical length of the directional coupler is obtained using
FIGURE 6.4 Coupled line mode representation: (a) even mode; (b) odd mode.
FIGURE 6.4 Coupled line mode representation: (a) even mode; (b) odd mode.
C,, represents the capacitance in the odd mode for the fringing field across the gap in the dielectric region. It can be found using
C,, represents the capacitance in the odd mode for the fringing field across the gap in the dielectric region. It can be found using
coupler performance is compared with the planar electromagnetic simulators such as Sonnet and Ansoft Designer. It is shown that the results are in close agreement, and the method can be used for applications that require accuracy. The step-by-step design procedure to implement three-line couplers is as follows:
coupler performance is compared with the planar electromagnetic simulators such as Sonnet and Ansoft Designer. It is shown that the results are in close agreement, and the method can be used for applications that require accuracy. The step-by-step design procedure to implement three-line couplers is as follows:
FIGURE 6.6 MATLAB GUI for a two-line microstrip directional coupler. SR eae anne SERS ARR ee ee ee The simulation results showing the coupling level of Teflon at 300 MHz for a two-line microstrip directional coupler are illustrated in Figure 6.8 and are equal to 14.66 dB. Following the design procedure to realize a three-line microstrip cou- pler and obtain its physical dimensions as has been done with a MATLAB GUI and shown in Figure 6.9, a three-line microstrip directional coupler is then simulated with Ansoft Designer, as shown in Figure 6.10.
FIGURE 6.6 MATLAB GUI for a two-line microstrip directional coupler. SR eae anne SERS ARR ee ee ee The simulation results showing the coupling level of Teflon at 300 MHz for a two-line microstrip directional coupler are illustrated in Figure 6.8 and are equal to 14.66 dB. Following the design procedure to realize a three-line microstrip cou- pler and obtain its physical dimensions as has been done with a MATLAB GUI and shown in Figure 6.9, a three-line microstrip directional coupler is then simulated with Ansoft Designer, as shown in Figure 6.10.
FIGURE 6.7 Simulated two-line microstrip directional coupler.
FIGURE 6.7 Simulated two-line microstrip directional coupler.
FIGURE 6.8 Simulated results for the coupling level for a two-line symmetrical coupler.
FIGURE 6.8 Simulated results for the coupling level for a two-line symmetrical coupler.
FIGURE 6.9 MATLAB GUI for a three-line microstrip directional coupler.
FIGURE 6.9 MATLAB GUI for a three-line microstrip directional coupler.
FIGURE 6.10 Simulated three-line microstrip directional coupler.
FIGURE 6.10 Simulated three-line microstrip directional coupler.
FIGURE 6.11 Simulated results for the coupling level for a two-line symmetrical coupler.
FIGURE 6.11 Simulated results for the coupling level for a two-line symmetrical coupler.
FIGURE 6.12 Multilayer two-line, four-port microstrip directional coupler.
FIGURE 6.12 Multilayer two-line, four-port microstrip directional coupler.
The multilayer directional coupler is then implemented using Ansoft Designer, as shown in Figure 6.14.
The multilayer directional coupler is then implemented using Ansoft Designer, as shown in Figure 6.14.
FIGURE 6.14 Simulated three-line, multilayer planar directional coupler.
FIGURE 6.14 Simulated three-line, multilayer planar directional coupler.
FIGURE 6.17 Simulated results for the directivity level for multilayer coupler.
FIGURE 6.17 Simulated results for the directivity level for multilayer coupler.
FIGURE 6.18 Four-port transformer directional coupler. The performance of a four-port coupler can be calculated using S,, and S,, for coupling, isolation, and directivity levels when the excitation is from port | on the main line. In Figure 6.18, 7, is the transformer with turns ratio N,:1, and 7; is the transformer with turns ratio N,:1. The transformers are assumed to be ideal and
FIGURE 6.18 Four-port transformer directional coupler. The performance of a four-port coupler can be calculated using S,, and S,, for coupling, isolation, and directivity levels when the excitation is from port | on the main line. In Figure 6.18, 7, is the transformer with turns ratio N,:1, and 7; is the transformer with turns ratio N,:1. The transformers are assumed to be ideal and
FIGURE 6.19 Four-port transformer directional coupler for circuit analysis.
FIGURE 6.19 Four-port transformer directional coupler for circuit analysis.
IGURE 6.23 MATLAB GUI results for six-port coupler.
IGURE 6.23 MATLAB GUI results for six-port coupler.
FIGURE 6.26 Simulated circuit of six-port coupler using Ansoft Designer for frequency- domain analysis in reverse mode.
FIGURE 6.26 Simulated circuit of six-port coupler using Ansoft Designer for frequency- domain analysis in reverse mode.
FIGURE 6.29 Time-domain simulation results showing port voltages for six-port coupler using PSpice in forward mode.
FIGURE 6.29 Time-domain simulation results showing port voltages for six-port coupler using PSpice in forward mode.
The GUI window showing the parameters, inductance value, and all other design parameters including the physical length of the winding wire required to construct stacked inductor configuration is shown in Figure 6.31. Hence, the transformer that is designed should now be able to produce the required coupling level for the operating conditions in the forward and reverse modes at the center
The GUI window showing the parameters, inductance value, and all other design parameters including the physical length of the winding wire required to construct stacked inductor configuration is shown in Figure 6.31. Hence, the transformer that is designed should now be able to produce the required coupling level for the operating conditions in the forward and reverse modes at the center
FIGURE 6.32 Toroidal design and characterization program for the six-port coupler induc- tor design. (a) Layout of six-port coupler and (b) constructed six-port coupler.
FIGURE 6.32 Toroidal design and characterization program for the six-port coupler induc- tor design. (a) Layout of six-port coupler and (b) constructed six-port coupler.
Six-Port Transformer Coupler Performance Parameter Comparison
Six-Port Transformer Coupler Performance Parameter Comparison
FIGURE 6.35 The broadband frequency response of six-port coupler coupling, isolation, and directivity measurements in (a) forward and (b) reverse modes.
FIGURE 6.35 The broadband frequency response of six-port coupler coupling, isolation, and directivity measurements in (a) forward and (b) reverse modes.
EEE In this section, the analysis of multistate reflectometers based on a four-port network and a variable attenuator proposed in Ref. [42] and shown in Figure 6.36 is extended to examine the more general theory of using scalar power measure- ments to determine the complex reflection coefficient. The explicit closed-form relations and solutions for the system of equations are derived and used to calculate
EEE In this section, the analysis of multistate reflectometers based on a four-port network and a variable attenuator proposed in Ref. [42] and shown in Figure 6.36 is extended to examine the more general theory of using scalar power measure- ments to determine the complex reflection coefficient. The explicit closed-form relations and solutions for the system of equations are derived and used to calculate
FIGURE 6.39 Illustration of RF power sensor. RF power sensors measure the forward and reflected power of a signal connected to a load. The high-level overview can be seen in Figure 6.39. The signal is received at the input and travels along a 50-Q microstrip transmission line. It is then split using a coupled-line directional coupler, sending the signal through matching networks and into the logarithmic diode RF power detector, as well as the module and phase detec- tor. The output at both steps is filtered for anti-aliasing before entering the controller unit. The analog signal is converted to a digital signal, so the digital signal processor can perform the calibration techniques required to compensate for inaccuracies. The microcontroller should be able to communicate the calibrated information to a GUI and an Internet server, where it can be displayed both numerically and graphically. The block diagram of the implementation of the power sensor is given in Figure 6.40.
FIGURE 6.39 Illustration of RF power sensor. RF power sensors measure the forward and reflected power of a signal connected to a load. The high-level overview can be seen in Figure 6.39. The signal is received at the input and travels along a 50-Q microstrip transmission line. It is then split using a coupled-line directional coupler, sending the signal through matching networks and into the logarithmic diode RF power detector, as well as the module and phase detec- tor. The output at both steps is filtered for anti-aliasing before entering the controller unit. The analog signal is converted to a digital signal, so the digital signal processor can perform the calibration techniques required to compensate for inaccuracies. The microcontroller should be able to communicate the calibrated information to a GUI and an Internet server, where it can be displayed both numerically and graphically. The block diagram of the implementation of the power sensor is given in Figure 6.40.
FIGURE 6.40 Block diagram of the implementation of RF power sensor.
FIGURE 6.40 Block diagram of the implementation of RF power sensor.
The solution of Equations 6.135 through 6.138 yields three complex constants A, B, and C, which define the system. However, these calculations are performed in an embedded application using a microcontroller in power sensor, so it is desir- able to minimize the total number of operations needed to compute I’... This is done
The solution of Equations 6.135 through 6.138 yields three complex constants A, B, and C, which define the system. However, these calculations are performed in an embedded application using a microcontroller in power sensor, so it is desir- able to minimize the total number of operations needed to compute I’... This is done
Equation 6.139 shows the relationship between the four calibration parameters A, A,, A,, and A, and the measured value N. This simplification eliminates the need to perform three divisions in calculating A, B, and C, which are costly operations in a microcontroller. The load reflection coefficient may now be obtained from the load reflection coefficient by Equation 6.140, where Z) is the system reference impedance, which is generally 50 Q.
Equation 6.139 shows the relationship between the four calibration parameters A, A,, A,, and A, and the measured value N. This simplification eliminates the need to perform three divisions in calculating A, B, and C, which are costly operations in a microcontroller. The load reflection coefficient may now be obtained from the load reflection coefficient by Equation 6.140, where Z) is the system reference impedance, which is generally 50 Q.
FIGURE 6.41 Illustration of RF power sensor calibration.
FIGURE 6.41 Illustration of RF power sensor calibration.
ude ripples 1n the passband. Elliptic filters have steeper transition from passband to stopband similar Chebyshev filters and exhibit equal amplitude ripples in the passband and stopbat 2F/microwave filters and filter components can be represented using a two-pi 1etwork shown in Figure 7.3. The network analysis can be conducted using ABC yarameters for each filter. The filter elements can be considered as cascaded comfy 1ents, and hence, the overall ABCD parameter of the network is just a simple mat nultiplication of the ABCD parameter for each element. The characteristics of t ilter in practice are determined via insertion loss, S,,, and return loss, S,,. ABC yarameters can be converted to scattering parameters, and insertion loss and retu oss for the filter can be determined. The detailed analysis procedure for filters | een given in Ref. [1].
ude ripples 1n the passband. Elliptic filters have steeper transition from passband to stopband similar Chebyshev filters and exhibit equal amplitude ripples in the passband and stopbat 2F/microwave filters and filter components can be represented using a two-pi 1etwork shown in Figure 7.3. The network analysis can be conducted using ABC yarameters for each filter. The filter elements can be considered as cascaded comfy 1ents, and hence, the overall ABCD parameter of the network is just a simple mat nultiplication of the ABCD parameter for each element. The characteristics of t ilter in practice are determined via insertion loss, S,,, and return loss, S,,. ABC yarameters can be converted to scattering parameters, and insertion loss and retu oss for the filter can be determined. The detailed analysis procedure for filters | een given in Ref. [1].
Binomial filter response can be explained using Figure 7.4 for a two-element LPF network. Source impedance and cut-off frequency for the circuit in Figure 7.4 are assumed to be | Q and 1 rad/s, respectively. In the LPF network, N = 2, and power loss becomes 7.2.1.1 Binomial Filter Response
Binomial filter response can be explained using Figure 7.4 for a two-element LPF network. Source impedance and cut-off frequency for the circuit in Figure 7.4 are assumed to be | Q and 1 rad/s, respectively. In the LPF network, N = 2, and power loss becomes 7.2.1.1 Binomial Filter Response
where x = w/w,. The attenuation curves for Chebyshev LPF response are obtained from
where x = w/w,. The attenuation curves for Chebyshev LPF response are obtained from
The attenuation curves are obtained and given for several ripple values using MATLAB in Ref. [1] with examples. Example—F/2 LPF Design for RF Power Amplifiers Design an F/2 filter for an RF power amplifier that is operating at 13.56 MHz. The filter should have no impact during the normal operation of the amplifier. It should have at least 20-dB attenuation at F/2 frequency. The passband ripple should not exceed 0.1-dB ripple. It is given that the amplifier is presenting 30-Q impedance to load line. Solution
The attenuation curves are obtained and given for several ripple values using MATLAB in Ref. [1] with examples. Example—F/2 LPF Design for RF Power Amplifiers Design an F/2 filter for an RF power amplifier that is operating at 13.56 MHz. The filter should have no impact during the normal operation of the amplifier. It should have at least 20-dB attenuation at F/2 frequency. The passband ripple should not exceed 0.1-dB ripple. It is given that the amplifier is presenting 30-Q impedance to load line. Solution
The final LPF circuit having Chebyshev filter response is shown in Figure 7.9. The final circuit shown in Figure 7.9 is analyzed using network parameters, and insertion loss is obtained using ABCD parameters for the cascaded components as previously discussed: and is shown in Figures 7.10 and 7.11. The passband ripple is less than 0.1 dB, and the cut-off frequency is around 9 MHz, as shown in Figure 7.10. In addition, we have more than 25-dB attenua- tion at 13.56 MHz, as illustrated in Figure 7.11. The circuit is simulated with Ansoft Designer for accuracy using the circuit shown in Figure 7.12. The passband ripple, attenuation at cut-off frequency, and operational frequency are given in Figure 7.13 and are in agreement with the MATLAB results obtained.
The final LPF circuit having Chebyshev filter response is shown in Figure 7.9. The final circuit shown in Figure 7.9 is analyzed using network parameters, and insertion loss is obtained using ABCD parameters for the cascaded components as previously discussed: and is shown in Figures 7.10 and 7.11. The passband ripple is less than 0.1 dB, and the cut-off frequency is around 9 MHz, as shown in Figure 7.10. In addition, we have more than 25-dB attenua- tion at 13.56 MHz, as illustrated in Figure 7.11. The circuit is simulated with Ansoft Designer for accuracy using the circuit shown in Figure 7.12. The passband ripple, attenuation at cut-off frequency, and operational frequency are given in Figure 7.13 and are in agreement with the MATLAB results obtained.
Pee Se Sane Se! EO Se SN SS ee 2S ee See Oe See eee ee The input impedance for the filter designed is given in Figure 7.14. Based on the results on the Smith chart, the filter input impedance is (29.58 — /8.48) Q at F/2 and (0.06 + j43.02) Q. Hence, the filter presents a very closely matched load to the amplifier at F/2 and terminates the F/2 frequency content; moreover, it pres- ents inductance, acts like an open load at the operational frequency, and does not have any impact on amplifier performance.
Pee Se Sane Se! EO Se SN SS ee 2S ee See Oe See eee ee The input impedance for the filter designed is given in Figure 7.14. Based on the results on the Smith chart, the filter input impedance is (29.58 — /8.48) Q at F/2 and (0.06 + j43.02) Q. Hence, the filter presents a very closely matched load to the amplifier at F/2 and terminates the F/2 frequency content; moreover, it pres- ents inductance, acts like an open load at the operational frequency, and does not have any impact on amplifier performance.
The term (@,5 — @,)/@o is called the fractional bandwidth, and @y is called the reso- nant or center frequency, and ®,, and @,, are the upper and lower cut-off frequencies, respectively. The transformation given by Equation 7.26 maps the series component of an LPF prototype circuit to a series LC circuit and the shunt component of an LPF prototype circuit to a shunt LC circuit in the BPF. The component values of the series LC circuit are calculated as
The term (@,5 — @,)/@o is called the fractional bandwidth, and @y is called the reso- nant or center frequency, and ®,, and @,, are the upper and lower cut-off frequencies, respectively. The transformation given by Equation 7.26 maps the series component of an LPF prototype circuit to a series LC circuit and the shunt component of an LPF prototype circuit to a shunt LC circuit in the BPF. The component values of the series LC circuit are calculated as
The two-port Z-parameter matrix for a transmission line in Figure 7.18 is
The two-port Z-parameter matrix for a transmission line in Figure 7.18 is
Consider the case when characteristic impedance Z) is very high. This impedance is denoted as Z,;.,. For the shunt component, since Bé is very small, the impedance will be very large. In fact, it can be considered an open circuit. This results in an approximate circuit impedance of series component, jZ,;.,B¢, as
Consider the case when characteristic impedance Z) is very high. This impedance is denoted as Z,;.,. For the shunt component, since Bé is very small, the impedance will be very large. In fact, it can be considered an open circuit. This results in an approximate circuit impedance of series component, jZ,;.,B¢, as
High impedance condition transforms the 7T-network to equivalent series- connected L-network, as shown in Figure 7.21. Now, consider the case when the characteristic impedance is low (Z,,,,). This time, the series components have a very low impedance and can be considered shorted. The resulting approximate circuit impedance is that of the shunt component alone or Z,,,, /B€ as impedance is that of the shunt component alone or Z,,,, /Pé as
High impedance condition transforms the 7T-network to equivalent series- connected L-network, as shown in Figure 7.21. Now, consider the case when the characteristic impedance is low (Z,,,,). This time, the series components have a very low impedance and can be considered shorted. The resulting approximate circuit impedance is that of the shunt component alone or Z,,,, /B€ as impedance is that of the shunt component alone or Z,,,, /Pé as
FIGURE 7.21 High-impedance transformation of T-network.
FIGURE 7.21 High-impedance transformation of T-network.
4 STEPPED-IMPEDANCE RESONATOR BPFs Conventional parallel-coupled BPFs suffer drastically from spurious harmonics. The stepped-impedance resonator (SIR) filters can be used to realize high-performance BPFs by suppressing the spurious harmonics to overcome this problem. One of the key features of an SIR is that its resonant frequencies can be tuned by adjusting the impedance ratios of the high-Z and low-Z sections. The symmetrical tri-section SIR used in the BPF design is shown 1 in in Figure 123: a, en ae cae a... a ee as Re ne, ae ee eo i ee See (er are er a 7 Then, the impedance limit for Z,,,, is
4 STEPPED-IMPEDANCE RESONATOR BPFs Conventional parallel-coupled BPFs suffer drastically from spurious harmonics. The stepped-impedance resonator (SIR) filters can be used to realize high-performance BPFs by suppressing the spurious harmonics to overcome this problem. One of the key features of an SIR is that its resonant frequencies can be tuned by adjusting the impedance ratios of the high-Z and low-Z sections. The symmetrical tri-section SIR used in the BPF design is shown 1 in in Figure 123: a, en ae cae a... a ee as Re ne, ae ee eo i ee See (er are er a 7 Then, the impedance limit for Z,,,, is
FIGURE 7.24 Triple-band BPF using SIRs. The width of the sections in the SIR is obtained from Equations 7.55 through 7.57. The performance of BPFs with SIRs can be improved by using the configuration given in Figure 7.24. The BPF in Figure 7.24 provides triple-band filter character- istics with the coupling scheme shown in Figure 7.25. In Figure 7.24, the coupled lines’ equivalent circuit is represented by two single transmission lines of electrical length 0, characteristic impedance Zp, and admittance inverter parameter J, as shown in Figure 7.26. Inverter parameter J is an important design parameter because it is directly proportional to the coupling strength of the coupled lines.
FIGURE 7.24 Triple-band BPF using SIRs. The width of the sections in the SIR is obtained from Equations 7.55 through 7.57. The performance of BPFs with SIRs can be improved by using the configuration given in Figure 7.24. The BPF in Figure 7.24 provides triple-band filter character- istics with the coupling scheme shown in Figure 7.25. In Figure 7.24, the coupled lines’ equivalent circuit is represented by two single transmission lines of electrical length 0, characteristic impedance Zp, and admittance inverter parameter J, as shown in Figure 7.26. Inverter parameter J is an important design parameter because it is directly proportional to the coupling strength of the coupled lines.
These even- and odd-mode impedances are directly used to find the dimensions of the microstrips in the BPF. After the even- and odd-mode impedances are deter- mined, the synthesis technique introduced in Refs. [1,2] and in Chapter 6 is used to determine accurate physical dimensions. Based on the synthesis method, the spacing ratio between coupled lines is found using coupled microstrip lines. These values are also calculated in the MATLAB script from the following equations:
These even- and odd-mode impedances are directly used to find the dimensions of the microstrips in the BPF. After the even- and odd-mode impedances are deter- mined, the synthesis technique introduced in Refs. [1,2] and in Chapter 6 is used to determine accurate physical dimensions. Based on the synthesis method, the spacing ratio between coupled lines is found using coupled microstrip lines. These values are also calculated in the MATLAB script from the following equations:
The physical length of the directional coupler is obtained using
The physical length of the directional coupler is obtained using
FIGURE 7.29 BPF with final lumped element component values.
FIGURE 7.29 BPF with final lumped element component values.
FIGURE 7.30 BPF simulation results with Ansoft Designer.
FIGURE 7.30 BPF simulation results with Ansoft Designer.
Even- and Odd-Mode Impedance Values
Even- and Odd-Mode Impedance Values
The frequency response of the lumped element BPF is also obtained with the program and is shown in Figure 7.31. The results obtained in Figure 7.31 match the results obtained with Ansoft Designer. The physical dimensions calculated with the MATLAB program given are used to simulate the microstrip edge-coupled filter with Sonnet planar electromagnetic simulator, as shown in Figure 7.32.
The frequency response of the lumped element BPF is also obtained with the program and is shown in Figure 7.31. The results obtained in Figure 7.31 match the results obtained with Ansoft Designer. The physical dimensions calculated with the MATLAB program given are used to simulate the microstrip edge-coupled filter with Sonnet planar electromagnetic simulator, as shown in Figure 7.32.
FIGURE 7.36 Layout of microstrip gap for Sonnet simulation. The gap dimensions can be calculated using the closed-form expressions given. Planar electromagnetic simulators can also be utilized to obtain the capacitance val- ues shown in Figure 7.35 with simulation of a two-port microstrip gap shown in Figure 7.36. The two-port parameters can be obtained from the simulation and can be represented in Y parameters as
FIGURE 7.36 Layout of microstrip gap for Sonnet simulation. The gap dimensions can be calculated using the closed-form expressions given. Planar electromagnetic simulators can also be utilized to obtain the capacitance val- ues shown in Figure 7.35 with simulation of a two-port microstrip gap shown in Figure 7.36. The two-port parameters can be obtained from the simulation and can be represented in Y parameters as
FIGURE 7.39 Equivalent BPF schematic.
FIGURE 7.39 Equivalent BPF schematic.
FIGURE 7.40 Insertion loss of the equivalent BPF.
FIGURE 7.40 Insertion loss of the equivalent BPF.
In order to determine the length of each capacitive gap and the value of each parallel capacitor, several simulations of different gap lengths are performed using Sonnet with the configuration shown in Figure 7.35. In the simulation, the width of the microstrip is set to 1.1 mm, and its thickness is taken to be 1.27 mm. The dielec- tric constant of the material is given to be 10.8. The Y parameters of the microstrip, operating at 6 GHz, are extracted for each simulation. In addition, the series and parallel capacitor values are calculated using Equations 7.96 and 7.97. The results are shown in Table 7.4. KRlaceé tha wT and wea hen Alkeboatwend Dem Thhhe 7 A memecunladciad ax wehnccm Se Boa’ 7 AT
In order to determine the length of each capacitive gap and the value of each parallel capacitor, several simulations of different gap lengths are performed using Sonnet with the configuration shown in Figure 7.35. In the simulation, the width of the microstrip is set to 1.1 mm, and its thickness is taken to be 1.27 mm. The dielec- tric constant of the material is given to be 10.8. The Y parameters of the microstrip, operating at 6 GHz, are extracted for each simulation. In addition, the series and parallel capacitor values are calculated using Equations 7.96 and 7.97. The results are shown in Table 7.4. KRlaceé tha wT and wea hen Alkeboatwend Dem Thhhe 7 A memecunladciad ax wehnccm Se Boa’ 7 AT
FIGURE 7.42 C, vs. gap length from simulation. The equation of the line is used to obtain the length of the gap by interpolation. In the equation on the graph, x corresponds to known capacitance, and y is the cor- responding gap length. A similar approach is taken to determine the capacitance C, terms for each equivalent gap. The interpolation gives the value of the corresponding capacitance for C, as shown in Figure 7.42. The summary of the calculated gap leneths and corresponding capacitance val- Summary of the Calculated Lengths and Capacitance Values
FIGURE 7.42 C, vs. gap length from simulation. The equation of the line is used to obtain the length of the gap by interpolation. In the equation on the graph, x corresponds to known capacitance, and y is the cor- responding gap length. A similar approach is taken to determine the capacitance C, terms for each equivalent gap. The interpolation gives the value of the corresponding capacitance for C, as shown in Figure 7.42. The summary of the calculated gap leneths and corresponding capacitance val- Summary of the Calculated Lengths and Capacitance Values
FIGURE 7.44 Simulation results for end-coupled microstrip BPF using Sonnet. physical values calculated using the generic MATLAB script developed and given below with the results shown in Table 7.5. The Sonnet simulation circuit layout with physical dimensions is illustrated in Figure 7.43. The simulation results for insertion and return losses are given in Figure 7.44.
FIGURE 7.44 Simulation results for end-coupled microstrip BPF using Sonnet. physical values calculated using the generic MATLAB script developed and given below with the results shown in Table 7.5. The Sonnet simulation circuit layout with physical dimensions is illustrated in Figure 7.43. The simulation results for insertion and return losses are given in Figure 7.44.
FIGURE 8.6 Transformation from (a) a-network to (b) L-network.
FIGURE 8.6 Transformation from (a) a-network to (b) L-network.
FIGURE 8.7, MATLAB GUI output for three-way unbalanced combiner when 0 = 90°. The corresponding component values of the lumped elements for the L-network given in Figure 8.6b are
FIGURE 8.7, MATLAB GUI output for three-way unbalanced combiner when 0 = 90°. The corresponding component values of the lumped elements for the L-network given in Figure 8.6b are
AMD is the arithmetic mean distance, and GMD is used for the geometric dis- tance. C is the capacitance that includes the effect of odd mode, even mode, and interline coupling capacitances between coupled lines of the spiral inductor. The detailed calculation of the capacitances is given in Ref. [9]. The substrate losses and conductor losses are ignored due to the low operational frequency. The one-port measurement network for the spiral inductor using the model pro-
AMD is the arithmetic mean distance, and GMD is used for the geometric dis- tance. C is the capacitance that includes the effect of odd mode, even mode, and interline coupling capacitances between coupled lines of the spiral inductor. The detailed calculation of the capacitances is given in Ref. [9]. The substrate losses and conductor losses are ignored due to the low operational frequency. The one-port measurement network for the spiral inductor using the model pro-
FIGURE 8.11. 3D model of the simulated spiral inductor. Physical Dimensions of the Spiral Inductor The traces, as seen in Figure 8.1 stand the effect of width and spacing on t factor of the spiral inductor. One of the unique features of t he self-resonant , are segmented for parametric study to under- frequency and the quality he planar electromagnetic simulator is the visualization of the current distribution on the spiral structure. This is speci fically important for high-power a between traces to prevent any possible arc 8.12, the current density on the brid on the d evice performance and overall ind pplications to adj increases as it gets closer to the edges o edges. This is why during the implementation of the spira rounded ust the necessary spacing during the operation. As seen from Figure ge, which is designed luctance, is the lowest. The current density f each trace. It becomes maximum at the to have minimal impact inductor, the corners are to increase the creepage distance to prevent potential arcs. The inductance value of the spiral inductor is simulated and obtained as 588.6 nH
FIGURE 8.11. 3D model of the simulated spiral inductor. Physical Dimensions of the Spiral Inductor The traces, as seen in Figure 8.1 stand the effect of width and spacing on t factor of the spiral inductor. One of the unique features of t he self-resonant , are segmented for parametric study to under- frequency and the quality he planar electromagnetic simulator is the visualization of the current distribution on the spiral structure. This is speci fically important for high-power a between traces to prevent any possible arc 8.12, the current density on the brid on the d evice performance and overall ind pplications to adj increases as it gets closer to the edges o edges. This is why during the implementation of the spira rounded ust the necessary spacing during the operation. As seen from Figure ge, which is designed luctance, is the lowest. The current density f each trace. It becomes maximum at the to have minimal impact inductor, the corners are to increase the creepage distance to prevent potential arcs. The inductance value of the spiral inductor is simulated and obtained as 588.6 nH
Trace Width w
Trace Width w
FIGURE 8.13 Simulated three-way combiner in planar form using L-network topology.
FIGURE 8.13 Simulated three-way combiner in planar form using L-network topology.
FIGURE 8.15 VSWR vs. frequency for three-way microstrip combiner.
FIGURE 8.15 VSWR vs. frequency for three-way microstrip combiner.
FIGURE 8.16 Three-way combiner implemented in planar.
FIGURE 8.16 Three-way combiner implemented in planar.
JRE 8.17. Three-way combiner implemented in planar.
JRE 8.17. Three-way combiner implemented in planar.
FIGURE 8.23 Simulated bond inductance value for three parallel bond wires.
FIGURE 8.23 Simulated bond inductance value for three parallel bond wires.
FIGURE 8.24 Simulated source lead inductance vs. frequency.
FIGURE 8.24 Simulated source lead inductance vs. frequency.
GURE 8.27 Cosimulation of four-die hybrid package for parasitics with bond wires. complete hybrid package simulation is illustrated in Figures 8.26 and 8.27. Figure 8.26 gives the 2D and 3D layout of the structure that is simulated. Figure 8.27 is the circuit when the bond wires are included to the structure that is simulated and is shown in Figure 8.26. Cosimulation technique is used to simulate both electromag- netic structure and bond wires using Ansoft Designer.
GURE 8.27 Cosimulation of four-die hybrid package for parasitics with bond wires. complete hybrid package simulation is illustrated in Figures 8.26 and 8.27. Figure 8.26 gives the 2D and 3D layout of the structure that is simulated. Figure 8.27 is the circuit when the bond wires are included to the structure that is simulated and is shown in Figure 8.26. Cosimulation technique is used to simulate both electromag- netic structure and bond wires using Ansoft Designer.
FIGURE 8.28 Simulated four-die hybrid package parasitics.
FIGURE 8.28 Simulated four-die hybrid package parasitics.

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