Academia.edu no longer supports Internet Explorer.
To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser.
2004, IEEE Transactions on Circuits and Systems I: Regular Papers
where the output voltage at the termination point of the transmission line may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing. This is in sharp contrast with the steady state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay and the percentage of maximum undershoot when the circuit exhibits an underdamped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product. The experimental results carried out by HSPICE simulation verify the accuracy of our models.
2003
Abstract This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing.
To obtain higher performance with maximum devices and smaller chip size semiconductor devices are continuously shrinking. However, leakage power dissipation increases significantly with the technology scaling. Increasing demand for ultra low power devices has increased significantly since last decade and it compels advance technological solutions to fulfill power requirements of electronic appliances. As a result subthreshold operation region and different device optimization techniques attracts different researchers to achieve ultra low power design of VLSI circuits. Power supply reduction is supposed to be the main parameter to reduce power reduction. However, deep subthreshold region offers speed penalty degrading the overall performance of a device which suggests the need for optimizing device parameters. This paper analyzes the driver and interconnects performance by changing threshold voltage (V th ) and oxide thickness (T ox ) in subthreshold region. Further, it also compares the optimized driver performance and DTMOS driver performance at 0.4 V. Moreover, a large amount of gain in performance was observed when optimized interconnect is used with the optimized driver. Result shows that performance of a circuit enhances if the optimized driver is used compared to DTMOS driver.
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
Journal of Low Power …, 2008
It is now well admitted that interconnects introduce delays and consume power and chip resources. To deal with these problems, some studies have been done on performance optimization. However, as the results presented in this paper show, such techniques are not based on good criteria for interconnect performance optimizations. We have, therefore, developed a high-level estimation tool based on transistor-level characteristics, which provides fast and accurate figures for both time and power consumption. These results allowed us to create a new interconnect consumption model and also to determine new key issues that have to be taken into account for future performance optimizations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.
2021
Abstract: Digital system’s performance is measured with respect to the power, delay and area. Area and the speed of operation are the two most conflicting design constraints. Hence increasing the speed of operation enhances the area requirement. The power consumption and delay of a particular circuit depends upon the supply voltage (VDD). A slight increment in the supply voltage increases the overall power consumption but at the same time it decreases the delay of the circuit. The paper has explained the trade-off between different design constraints in VLSI/ULSI circuits. The paper also explains the requirement of low-power design & the causes of power dissipation along with the factors affecting the high-speed.
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
Proceedings of the 39th conference on Design automation - DAC '02, 2002
The purpose of this work is two fold. First, to quantify and establish future trends for the dynamic power dissipation in global wires of high performance integrated circuits. Second, to develop a novel and efficient delay-power tradeoff formulation for minimizing power due to repeaters, which can otherwise constitute 50% of total global wire power dissipation. Using the closed form solutions from this formulation, power savings of 50% on repeaters are shown with minimal delay penalties of about 5% at the 50 nm technology node. These closed-form, analytical solutions provide a fast and powerful tool for designers to minimize power.
Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02, 2002
The impact of global on-chip interconnections on power consumption and speed of integrated circuits is becoming a serious concern. Designers need therefore to quickly estimate how performance and power are affected by a given choice of the interconnection parameters (length, voltage swing, driver and receiver schematics and sizing). This work focuses on the entire communication channel (driver, interconnect, receiver), and provides high level parametric VHDL simulation models for low-swing signaling schemes. These SPICE-derived power and timing macromodels transfer electrical-level information to the RTL simulation in an event-driven fashion, as transitions occur at the input of the interconnect driver. The accuracy reached by this backannotation technique is within 5% with respect to SPICE results, with only 4% simulation speed penalty in the worst case.
International J. of Recent Trends in …, 2010
This paper reviews different encoding schemes for reduction of power dissipation, crosstalk noise and delay. Crosstalk is aggravated by enhanced switching activity which is often main cause for the malfunctioning of any VLSI chip. Consequently, delay and power dissipation also increases due to enhanced crosstalk. Reduction in switching activities through coupled transmission line results in enormous reduction of power dissipation, crosstalk and delay. The researchers therefore often concentrate on encoding schemes that reduces the transitions of the signals. This paper reviews all such encoding schemes.
Proc. Int. Workshop Power and Timing Modeling …, 2001
We present a simple and accurate model to compute the power dissipated in sub-micron CMOS buffers driving RC interconnect lines. The expression obtained accounts for the main effects in current sub-micron CMOS technologies as carrier velocity saturation effects, input-output coupling capacitor, output load, input slew time, device sizes and interconnect resistance. Results are compared to HSPICE simulations (level 50) and other models for a 0.18µm and a 0.35µm technologies showing significant improvements.
In VLSI interconnect buffers are used to restore the signal level affected by the parasitics. However buffers have a certain switching time that contributes to overall signal delay. Further the transitions that occur in interconnects also contribute to crosstalk delay. Thus the overall delay in interconnects is due to combined effect of both buffer and crosstalk delay. In this work a replacement of buffers with Schmitt trigger is proposed for the same purpose of signal restoration. Due to lower threshold voltage of Schmitt trigger signal can rise early and the large noise margin of Schmitt trigger helps in reducing the noise glitches as well. Simulation results shows that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffers.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)
In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay constraint is proposed. The energy formulations are obtained by using approximated expressions for the driving-point impedance of lossy coupled transmission lines which itself is derived by solving Telegrapher's equations. A comprehensive analysis of energy is performed for a wide variety range of the gate aspect-ratios of the driving transistors. To accomplish this task, two stable circuits that are capable of modeling the transmission line for a broad range of frequencies are synthesized. Experimental results show that the energy calculated using these equivalent circuits are almost equal to the one calculated by solving the more complicated transmission line equations directly. Next, using a new performance metric the effect of geometrical variations of the interconnect and the driver on the energy optimization under the delay constraint is studied. The experimental results verify the accuracy of our models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-m TSMC CMOS technology and applied to a 4500-m long Metal4 bus. Circuit simulation results for different bus widths are presented.
2011 Second International Conference on Emerging Applications of Information Technology, 2011
As the size of transistor is decreasing, more number of functionalities are integrated onto a single chip, so the interconnect length is ever increasing. Signal rise time is decreasing as compared to the time of flight. Hence, the interconnect can no longer be modelled as RC tree, rather it must be modelled as a transmission line by taking the inductance into account. With the increase in frequency, the dynamic power dissipation associated with interconnect is also increasing. Hence, an efficient method to estimate the interconnect power dissipation is necessary. In this paper, a simple yet accurate method has been proposed to estimate dynamic power dissipation of on-chip interconnect. A reduced order model is derived. The proposed model is directly derived from total resistance, inductance and capacitance of interconnects. Through the analysis made in this paper, it is shown that the dynamic power dissipation for the interconnects can be accurately estimated. The results of the proposed method applied to various RLC networks show that maximum relative error is within 4 to 6% compared to the SPICE results.
2013
Ever increasing fraction of the energy consumption of an Integrated circuit is due to the interconnect wires (and the associated driver and receiver circuits). Power dissipation from the interconnect wires amounts to up to 40% of the total on-chip power dissipation in some gate array design styles. When compared with other techniques a diode-connected driver circuit has the best attributes over other low-swing signaling techniques in terms of power, and delay. The proposed signaling schemes of symmetric lowswing driver-receiver pairs (MJ-SIB) and (MJDB) for driving signals on the global interconnect lines, which are implemented using split R-π model for an interconnect line, provides best results.
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 2018
This paper resolves the performance issue encountered in very-large-scale integration interconnects due to downsizing of integrated circuits. Interconnects designed using carbon nanotubes (CNT) are compared with conventional copper interconnect. The propagation delay of very lengthy interconnect wires is ameliorated by interpolating smart buffers as repeaters within the wires. Existing buffer designs are contrived using both CNT and MOS technology for comparison using a different combination of MOS repeater-Cu interconnect and CNT repeater-CNT interconnect. Propound buffer uses power gating techniques and automated toggling approach to reduce delay besides mitigating average power consumption. Compared to conventional buffer, PropoundDesign3 brings about dynamic power saving of 99.94% and leakage power saving of 93%, but causes delay penalty. PropoundDesign2 saves dynamic power by 99.86% and leakage power by 88% and offers reduction in delay by 52%. Whereas PropoundDesign1 saves dynamic power by 98% and reduces propagation delay by 64% but on the cost of leakage power consumption. Simulation for 32 nm is done in HSPICE by considering a section of long interconnect line as driver interconnect load system using Stanford SPICE model for CNT and BSIM4 PTM for MOS.
IEEE Transactions on Electron Devices, 2004
This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes.
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS/X simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the shortcircuit to dynamic power is less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. Therefore, the total power consumption is expected to decrease as inductance effects becomes more significant as compared to an RC model of the interconnect.
Loading Preview
Sorry, preview is currently unavailable. You can download the paper by clicking the button above.