Electrical Engineering

The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shuntseries feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dB and an input-referred currentnoise spectral density of 39.8 pA/ √ H z over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm 2 (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).

This paper presents a 53-61GHz low-power chargepump integer-N type-II PLL, employing a class-D V-band VCO. Transistors in the VCO enter deep triode region to achieve low DC power and phase noise. Pros and cons of the triode region are studied in this paper. We have explained how this region has been accurately exploited to reduce the phase-noise. This is unlike the general notion that the triode region degrades phase-noise performance in oscillators. The PLL is fabricated in a standard 65nm CMOS process. The VCO consumes the minimum power of 10.6mW from 0.8V supply. The PLL achieves a wide tuning range of 13% from 53.35-to 60.83-GHz and a phase noise of -88 dBc/Hz at 1MHz offset, while consuming a minimum DC power of 48mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.

This paper presents the design of a high efficiency, low THD, 5.7GHz fully differential power amplifier for wireless communications in a standard 0.18µm CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injection-locked oscillator is utilized, which makes the output voltage of the power amplifier tuned at the input signal frequency. A complementary CMOS cross-coupled pair topology is employed to realize the LC-tank oscillator because it has lower phasenoise, thereby giving lower THD than the single NMOS cross-coupled pair topology. The proposed power amplifier can deliver 25dBm output power to a 50 load at 5.7GHz with 42.6% power-added efficiency (PAE) from 1.8V supply voltage.

MedRadio 413-419 MHz inductorless transceiver (TRX) for an implantable brain-machine interface (BMI) in a 180 nm CMOS process is presented. Occupying 5.29 mm 2 of die area (including pad ring), this on-off-keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and S11 of -13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42/92 µW power from 1.8 V supply at 1/10 kbps data-rates, achieving -79/-74 dBm sensitivities for 0.1% bit-error-rate (BER). The TX employs a current-starved ring oscillator with an automatic frequency calibration loop, covering 9% supply-voltage variation and 15-78 • C temperature range which guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at -4 dBm output power. Wireless testing over a 350 cm distance accounting for bio-signal data transfer, multi-user coexistence, and in-vitro phantom measurement results are demonstrated.

A 64-channel bioelectric signal acquisition system incorporating a CMOS ultra-low power amplifier array and serializer integrated circuit (IC) is presented. Each amplifier within the array employs a complementary differential topology with cross-coupled-pair active load to achieve ultra-low power and low-noise operation for a nominal gain of 39 dB. The serializer utilizes zero-power complementary switch network which is controlled by an on-chip synchronous counter-based control circuitry. Fabricated in a 130 nm CMOS process with an area of 5.45 mm 2 (excluding pads), the IC is designed to operate in the weak inversion region, resulting in an estimated total power consumption of 14 µW. Each amplifier consumes 216 nW from 0.4 V supply and occupies 0.044 mm 2 of die area. The measured input-referred voltage noise across 190 Hz of amplifier's bandwidth is 2.19 µVRMS, corresponding to a power efficiency factor of 11.7. Experiments show that this system effectively amplifies human electroencephalographic and electromyographic signals. Index Terms-Electrocorticography (ECoG), brain-computer interface, ultra-low power (ULP), noise efficiency factor (NEF), power efficiency factor (PEF), operational transconductance amplifier (OTA), weak inversion (WI) region.

A highly efficient push-push voltage controlled oscillator (VCO) with a new varactor-less-based frequencytuning topology for terahertz (THz) frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base degenerated transistor. Fabricated in a 130nm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and output power of ----7.2 dBm at 201.5GHz. The VCO consumes 30mW of DC power, resulting in a record-breaking power efficiency of 0.6%. To demonstrate the functionality of the tuning technique, three other VCO prototypes at different oscillation frequencies, including one operating at 222.7~229 GHz range, have been implemented.

The design of a millimeter-wave dual-band phaselocked frequency synthesizer in a 0.18µm SiGe BiCMOS technology is presented. All circuits except the voltage controlled oscillators (VCOs) are shared between the two bands. A W-band divide-by-3 frequency divider is used inside the loop after the VCOs to simplify division-ratio reconfiguration. The 0.9mm 2 synthesizer chip exhibits a locking range of 23.8-26.95/75.67-78.5GHz with a low power consumption of 50-75mW from a 2.5V supply. The closed-loop phase noise at 1MHz offset from the carrier is less than -100dBc/Hz in both bands. The proposed frequency synthesizer is suitable for integration in directconversion transceivers for K/W-band automotive radars and heterodyne receivers for 94GHz imaging applications.

The design of a CMOS 22-29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-m CMOS process, the RX front-end chip occupies a die area of 3 mm 2 . On-wafer measurements show a conversion gain of 35-38.1 dB, a noise figure of 5.5-7.4 dB, and an input return loss less than 14.5 dB in the 22-29-GHz automotive radar band. The phase noise of the constituent QVCO is 107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.

This paper presents the design of the first CMOS distributed active power combiners and splitters with wideband variable delay and gain. These circuits are the key components for use in multi-antenna (MA) ultra-wideband (UWB) point-to-point beamforming communication systems with multiple transmit and receive antennas. Two broadband circuit topologies for each active power combiner and splitter are proposed, one of which being fabricated in a 0.13-m CMOS process. The proposed fabricated distributed active power combiner and splitter operate across wide range of frequencies that cover the UWB frequency range from 3.1 to 10.6 GHz. The gain of each RF path of the power combiner and splitter is independently controllable from 15 to 6 dB and from 16 to 9.5 dB, respectively. The wideband variable delay of each RF path varies from 32 to 42 ps for the two-stage power combiner, and from 43 to 53 ps for the three-stage power splitter across the UWB frequency rang. Supplied from 1.8-V DC voltage, the power combiner and splitter consume 8.5 mA and 11.4 mA, respectively. Index Terms-Active power combiner, active power splitter, broadband delay, distributed circuit, multi-antenna (MA) transceiver, ultra-wideband (UWB).

This paper presents a W-band receiver chipset for passive millimeter-wave imaging in a 65 nm standard CMOS technology. The system comprises a direct-conversion receiver front-end with injection-locked tripler and a companion analog back-end for Dicke radiometer. The receiver design addresses the high 1/f noise issue in the advanced CMOS technology. An LO generation scheme using a frequency tripler is proposed to lower the PLL frequency, making it suitable for use in multi-pixel systems. In addition, the noise performance of the receiver is further improved by optimum biasing of transistors of the detector in moderate inversion region to achieve the highest responsivity and lowest NEP. The front-end chipset exhibits a measured peak gain of 35 dB, 3 dB BW of 12 GHz, NF of 8.9 dB, while consuming 94 mW. The baseband chipset has a measured peak responsivity ( ) of 6 KV/W and a noise equivalent power (NEP) of 8.54 pW Hz 1 2 . The two chipsets integrated on-board achieve a total responsivity of 16 MV/W and a calculated Dicke NETD of 1K with a 30 ms integration time.

An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and doublebalanced architectures is presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and the channel's thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power is studied. Experimental results verify the accuracy of the analytical model.

The technology of pre-saturated core fault current limiter (PCFCL) has a particular importance due to its instantaneous limitation of the fault current in electric power grids and keeping its value below the ratings of the switchgear or circuit breakers with a reasonable safety margin. In this paper, a design methodology of single-phase, simple non-superconducting magnetic coils, PCFCL is proposed based on extensive electromagnetic time-domain finite-element simulations taking into account the relative performances of the constructive design parameters. These controlled finite-element simulations allow fine realistic details, such as the nonlinear magnetic saturation behavior of the iron core to be included, and studying the effect on general performance during dynamic reactions of the system. Moreover, the dynamic behavior of PCFCL is characterized in terms of steady-state voltage drop across its terminals, counter emf induced on the DC coil terminals, and limitation factor of the fault current. Dual-core and single-core designs are investigated with a comparison of their ability of limiting the fault current. Results reveal that the dual-core design has a superior performance than that of the single-core one. Finally, a design methodology flowchart has been proposed which depends on the extensive simulation results of different PCFCL topologies and published experimental results, where changing either the governing constructive parameters or the magnetic iron core design are considered.

Quadcopters or Drones have multiple applications for different purpose such as investigation, assessment, exploration, rescue and decreasing the human strength in an adverse situation. Unmanned air vehicles (UAV) is designed with four propellers to resolve the issue of constancy however it will make the drone further more complex for the dynamic modelling and for the control system. In this research, smart controller is intended to regulate the attitude of drone. Simulation ideal model and fuzzy logic control approach is formulated to implement for four elementary motions i.e. roll, pitch, yaw, and height of our drone for the application of earthquake. The key objective of this research paper is to develop the anticipated output as compare to the desired input.

L’articolo presenta i principali risultati di esperimenti eseguiti su nodi trave-pilastro innovativi realizzati con struttura composta acciaio e calcestruzzo. Trattasi di cinque prove in cui altrettanti nodi a due vie in scala reale sono sottoposti a spostamenti pseudo-statici di tipo ciclico tali da indurre una condizione di sollecitazione di tipo sismico. Quattro nodi hanno le travi di tipologia mista acciaio e calcestruzzo ed un nodo e interamente in calcestruzzo armato normale per stabilire utili confronti. Per quanto riguarda i primi quattro, due nodi hanno i pilastri in c.a., un nodo e realizzato con pilastro con camicia di acciaio di sezione quadrata ed infine un nodo ha anche i pilastri in struttura reticolare mista. I risultati ottenuti sono analizzati criticamente e confrontati tra loro per poter trarre utili conclusioni sulla duttilita e sulla resistenza dei nodi innovativi nei confronti delle sollecitazioni di natura sismica.

Encontrar errores en las ultimas etapas del desarrollo del diseno de hardware es costoso. En particular, para una arquitectura de microprocesador, la falta de ambiguedad es una propiedad esencial. Los metodos formales pueden ayudar a los disenadores a identificar inconsistencias en las especificaciones de un sistema dado. Este articulo presenta una descripcion formal de un subconjunto del conjunto de instrucciones de la arquitectura Triangle Abstract Machine (TAM) en Z. TAM es una maquina abstracta adecuada para la implementacion de lenguajes de programacion tipo Algol estructurados en bloques, como Pascal, Modula , Oberon y Triangle. La arquitectura de TAM se basa en la pila, lo que simplifica la generacion de codigo. La notacion matematica de Z y la estructura de su esquema ayudan a describir instrucciones logicas y aritmeticas y tambien proporcionan mecanismos adecuados para modelar instrucciones complejas que acceden a registros, memorias y la pila. Esta investigacion propone un...

This paper presents the relevancy, design, and test results of a mobile electrical vehicle for the applications of testing and providing electromagnetic interferences in Wi-Fi signal in the band 2.4-2.5 GHz. The mobile device includes power electronics supplying a magnetron device for the interference. Propulsion of the mobile device is implemented by using a system of stepper motors. The mobile device is controlled with the help of the microcontroller ATmega 16. For the interfering part, it is necessary to design the power electronics to supply the magnetron from the battery. The power electronics interface between a battery and magnetron must be able to transfer output battery voltage 12 VDC to the variable output 4000 VAC and power around 1 kW. The magnetron is used as a source of electromagnetic interference high-frequency acting on targets, which operates in the band of Wi-Fi signal. In addition, the system must be able to control the direction and power of EMI interferences. The investigations of the power-efficiency of power inverter versus power density will be discussed and optimised here.

Providing wireless electrical power to an implantable medical device (IMD) is critical to an implant's efficacy. Wireless power transfer based on magnetic coupling is the primary approach to powering an IMD. Reducing the size and improving the efficiency are the two primary design goals for the power-harvesting component of an IMD. A pulse-width-modulated (PWM) boost converter converts a low-voltage AC power generated by a miniaturized receiving coil to a desired high-voltage DC power. However, in the traditional PWM boost converter, the switching frequency is much higher than the frequency of the input AC power.The high switching frequency not only dissipates more power on the switch, but also prevents the circuit from handling high-frequency input AC power. Consequently, a low switching frequency AC to DC boost converter is achieved by aligning the PWM signal with the input of the AC boost converter. The experimental verification of the optimal delay and duty cycle of the PWM control signal was made possible by a microcontroller based Printed Circuit Board (PCB) test platform that we re-designed using surface-mounts. This research attempts to prove that the converter significantly improves the conversion efficiency by reducing the dissipated power associated with the PWM switch.

The purpose of the study was to determine the effectiveness of a device developed based on the latest electronics to control the coordination of movements of the lower limbs of students with disabilities. Materials and methods. 34 students with disabilities were involved in the study. At the time of the experiment, they had functional disorders of the lower limbs as a result of injuries and received a doctor's permission to participate in the experiment. The research was conducted at the theoretical and empirical levels, using the following methods: analysis, synthesis, systematization, generalization, technical modeling, pedagogical testing, and mathematical statistics. Results. In the research process, a device was used, which was developed as part of the conducted research. The device consists of two rubber mats in which capacitive proximity sensors are placed. The test task involves recording the number of touches of rubber mats in 20 seconds. The information received from the sensors during the student's performance of the test task, namely the alternate touching of the rubber mat with the big toe, is sent to the microcontroller via an infrared communication line. The development uses a high-performance microcontroller ATMega 328P, which can support a wide range of sensors and generate information about the time and frequency of leg movements. The signals of the student's toes touching the rubber mats, received by capacitive sensors, are processed by a microcontroller and displayed on a PC through a serial connection and using the Arduino software, which allows reading the received information about the execution of movements. Under the conditions of the pedagogical experiment, we tried to determine the quality of the measurement results. According to the obtained numerical indicators, the numerical values of the test authenticity obtained by the traditional method of fixing the results by a specialist correspond to the value "low". The results of the validity calculations showed that the correlation between the test measurement results and the evaluation results using the developed device was optimal with a correlation coefficient greater than 0.6. Conclusions. The importance of a high level of development of the coordination of movements of the lower limbs of students with disabilities is determined by the need to develop this quality to ensure the effectiveness of their rehabilitation in the process of inclusive PE. The analysis of the obtained material allows us to state that the practical application of the inclusive PE device developed based on the latest electronics will allow scientifically based optimization of this process to ensure its effectiveness.

The purpose of the study was to determine the authenticity of the dynamic balance control device developed on the basis of modern trends in the field of electronic equipment for students with disabilities. Materials and methods. 32 students with disabilities, aged 18-24 years, I-III years of study, who received a doctor's permission to participate in testing and had vestibular disorders, were selected for the studied sample, in accordance with the provisions of voluntariness and anonymity. General scientific methods of gathering theoretical information, the method of technical modeling, pedagogical testing and methods of mathematical statistics were used. Results. A dynamic balance control device was developed on the basis of the most up-to-date electronic equipment and programming. The device consists of an integrated electronic unit, a programmable microcontroller system unit, and a PC. The information received by the capacitive sensors placed in the unit of the integrated electronic unit during the student's performance of the test task is processed in the unit of the programmable microcontroller system and transmitted via non-contact infrared communication lines to the PC where it is graphically presented. To establish the authenticity of testing using the developed device, reliability and validity coefficients were determined, which in numerical values reached a "high" level, in contrast to the test the results of which were recorded directly by the teacher and numerically corresponded to the limits of "low" and "medium". Conclusions. The dynamic balance control device presented in the work is designed using the most up-to-date electronic equipment and programming. Considering the importance of eliminating vestibular disorders and related dynamic balance disorders in students with disabilities, the use of the presented development of the control device in the practice of inclusive PE is aimed at ensuring the effectiveness of this process. The integration of a control device developed based on current trends in the field of electronic equipment into the inclusive physical education of students with disabilities is the basis for the development of new approaches in the process of dynamic balance testing based on objective assessment.

Recently, multiport multi-input and multi-output (MIMO) antenna technology has been the main focus of both manufacturers and researchers. So, their biggest challenge was to propose a small antenna that operates in broadband. We will be the primary contributors to the manufacturing process for this sort of antenna in this work, so we suggested a 4×4 MIMO antenna in a very compact size. As a result, the antenna dimensions are (W=16 mm, L=16 mm, H=1.6 mm) and it operates in millimeter bands ranging from 38 to 80 GHz, with a wide bandwidth of 42 GHz. This antenna was created using modern design principles, such as the Rubik's cube form. According to the results, we noticed that the performance of the parameters is good, as the reflection coefficient is <10 dB for all frequencies. In addition, the isolation transmission performance between ports is <-26 dB, the envelope correlation coefficient (ECC) is <0.0000234 between all ports, and the diversity gain (DG) ranges between ports from 9.99 to 10 dB. Moreover, the percentage of the total antenna efficiency and radiation ranges from 70 to 98%, while the projected antenna gain range from 6.9 to 9.5 dB. With all these positive results, the suggested antenna has become one of the critical components in most contemporary wireless systems.

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-m SiGe BiCMOS technology featuring 120-GHz and 100 GHz max . The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10 9 is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a 3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a 3.6-V supply voltage. Index Terms-Clock and data recovery (CDR), clock multiplier, phase detector, SiGe BiCMOS. I. INTRODUCTION K EY BUILDING block ICs operating beyond 40-Gb/s data rate, such as multiplexers, demultiplexers, or retiming flip-flops, have already been reported in the literature [1], [2]. Highly integrated ICs such as receivers and transmitters showing adequate system-level performance in terms of jitter, bit-error rate (BER), and signal integrity have been reported only recently [3]-[6] . However, the required performance is achieved at the expense of high power consumption, particularly when sufficient design margins are sought. This is mainly due to the frequency capabilities of today's production-level technologies, which seem to be marginal for such high operating speeds. As a consequence, half-rate clocking schemes are in general chosen over full-rate clocking schemes; full-rate schemes stress technology limits and are more power hungry than half-rate schemes. However, compared with full-rate architectures, half-rate architectures present several new challenges. Clock and data recovery (CDR) circuits require quadrature clocks and present difficult clock distribution because of higher fan-out. Half-rate architectures are also more sensitive to jitter generation and jitter tolerance requirements because the phase detector (PD) has higher latency and is very sensitive to clock duty cycle distortion and quadrature clock phase matching. Finally, time-division multiplexers do not include a final retiming stage operating on a single edge of the clock, and thus the half-rate clock duty cycle distortion directly impacts the serial data output duty cycle.

This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16GFC and consumes 385 m W/link.

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. This paper will first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower CE0 and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4 : 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a 3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over 100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the CE0 of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.

Wind energy is one of the fastest power generation technologies in the power generation industry and one of the most cost-effective methods of generating electrical power. For system reliability, improving highly appropriate wind speed forecasting methods is desirable. The wavelet transform is a powerful mathematical technique that converts an analyzed signal into a time-frequency representation. This technique helps forecast non-stationary time series. The objective is to evaluate the performance of the "DWT-Random Forest" model in predicting wind speed through a comparative analysis of performance metrics (MSE, RMSE, and MAPE) with similar studies. Our motivation is rooted in the pressing need to improve wind forecasting methods to optimize renewable energy generation. The method involved implementing the model, which presented performance metrics: MSE of 0.0099, RMSE of 0.0996, and MAPE of 0.0779. However, comparative analysis with previous studies reveals that our model demonstrates competitive performance. The main result of this study is the finding that the "DWT-Random Forest" model exhibits a respectable performance in predicting wind speed, although there is room for improvement.

The paper presents a conceptual, analytical platform with various pathogen detection applications based on a hybrid magnetic field source comprised of permanent magnets and solenoid coils fixed on the same magnetic yoke that acts as a magnetic flux concentrator. The magnetic field creates magnetization forces that guide functionalized paramagnetic microparticles through the volume of an analyte sample to capture targeted pathogens. The presence of bacteria is sensed with an additional electrical impedance spectroscopy (EIS) module attached to the system at high-frequency electrical fields. The magnetic field control is studied using mathematical modeling and numerical simulation in several geometry setups, coil excitation, and remanent flux density values.

Digital printing of organic photovoltaic devices is presented as a viable option for the creation of increasingly complex device structures. Fully printed organic tandem junction devices were made that show a perfect summation of the open circuit voltages of the subcells. These results show the feasibility of complete digitally printed device stacks providing product designers with unprecedented freedom of design for integration of a photovoltaic functionality in new products.

Digital printing of organic photovoltaic devices is presented as a viable option for the creation of increasingly complex device structures. Fully printed organic tandem junction devices were made that show a perfect summation of the open circuit voltages of the subcells. These results show the feasibility of complete digitally printed device stacks providing product designers with unprecedented freedom of design for integration of a photovoltaic functionality in new products.

This study presents a design of low noise figure, high gain LNA at 5.8 GHz with cascaded and cascoded techniques using inductive drain feedback that is applicable for the WiMAX 802.16 standard. The amplifier uses Pseudomorphic High Electron Mobility Transistor FHX76LP super HEMT low noise FET. The Ansoft Designer SV as an Electromagnetic (EM) simulator was used during the design process. The LNA was designed using the inductive drain feedback, inductive generation to the source and the T-network as a matching technique was used at the input and output terminal. The cascaded and cascoded Low Noise Amplifier (LNA) produced a gain (S21) of 43.94 dB and the Noise Figure (NF) of 0.61 dB. The input reflection (S11), output reflection (S22) and return loss (S12) are -10.65, -20.02 and -52.23 dB, respectively. The measured 3 dB bandwidth of 1.24 GHz has been achieved. The input sensitivity is -84 dBm exceeded the standards required by IEEE 802.16 has been observed.

This research present a design of a higher gain (68.94dB) for PHEMT LNA using an inductive drain feedback technique for wireless application at 5.8GHz. The amplifier it is implemented using PHEMT FHX76LP transistor devices. The designed circuit is simulated with Ansoft Designer SV. The LNA was designed using inductive drain feedback, inductive generation to the source, and the T-network as a matching technique was used at the input and output terminal. The low noise amplifier (LNA) provides a noise figure 0.64 dB and gain (S 21 ) of 68.94 dB. The output reflection (S 22 ), input reflection (s 11 ) and return loss (s 12 ) are -17.37 dB, -15.77 dB and -88.39 dB respectively. The measurement shows the stability were at 4.54 and 3-dB bandwidth of 1.72 GHz. The input sensitivity is -92 dBm exceeded the standards required by IEEE 802.16.

This research present a design of a higher  gain (66.38dB) for PHEMT LNA  using an inductive drain feedback technique for wireless application at 5.8GHz. The amplifier it is implemented using PHEMT FHX76LP transistor devices.  The designed circuit is simulated with  Ansoft Designer SV.  The LNA was designed using  T-network as a matching technique was used at the input and output terminal,  inductive generation to the source and an inductive drain feedback. The  low noise amplifier (LNA) using lumped-component provides a noise figure 0.64 dB and a gain (S21) of 68.94 dB. The output reflection (S22), input reflection (S11) and return loss (S12) are -17.37 dB, -15.77 dB and -88.39 dB respectively. The measurement shows the  stability was at  4.54 and 3-dB bandwidth of 1.72 GHz. While, the  low noise amplifier (LNA) using  Murata manufactured component provides a noise figure 0.60 dB and a gain (S21) of 66.38 dB. The output reflection (S22), input reflection (S11) and return loss (S12)...

This paper presents a design of a single LNA cascaded with double stage cascoded LNA amplifiers using an inductive drain feedback technique. The amplifier is implemented using superHEMT FHX76LP transistor devices. The designed circuit is simulated with Ansoft Designer SV. The LNA is designed by using an inductive drain feedback, inductive generation to the source, and the T-network as a matching technique which is which is used at the input and output terminals. The low noise amplifier (LNA) provides a gain (S 21 ) of 68.94 dB and the noise figure (NF) of 0.64 dB. The return loss (S 12 ) output reflection (S 22 ) and input reflection (S 11 ) are -88.39,-17.37 and -15.77 dB respectively. The measurement shows a 3-dB bandwidth of 1.72 GHz and stability are 4.54 more than 1 has been achieved. The input sensitivity is -92 dBm exceeded the standards required by IEEE 802.16.

This project presents a low noise and high gain cascoded LNA amplifier for direct conversion RF front end receiver architecture, which operates at 5.8 GHz unlicensed band. The LNA used Transistor FHX76LP superHEMT low noise FET. This LNA was designed and used inductive feedback and T-matching network consisting of lump reactive at the input and output of the LNA circuit. A single cascoded LNA design was built to meet the standard of IEEE 802.16. The cascoded LNA produced low noise figure of 0.83 dB with high gain of 26.26 dB. The S-parameter for the input reflection S 11 , output reflection S 22 , and return loss S 12 are of -11.05 dB, -10.5 dB and -30.92 dB respectively. The bandwidth measured is 1.56 GHz, while the input sensitivity is -82.6 dBm which is compliant WiMAX standards. The single stage LNA amplifier simulated using Ansoft Designer SV.

This study presents a design of low noise figure, high gain LNA at 5.8 GHz with cascaded and cascoded techniques using inductive drain feedback that is applicable for the WiMAX 802.16 standard. The amplifier uses Pseudomorphic High Electron Mobility Transistor FHX76LP super HEMT low noise FET. The Ansoft Designer SV as an Electromagnetic (EM) simulator was used during the design process. The LNA was designed using the inductive drain feedback, inductive generation to the source and the T-network as a matching technique was used at the input and output terminal. The cascaded and cascoded Low Noise Amplifier (LNA) produced a gain (S21) of 43.94 dB and the Noise Figure (NF) of 0.61 dB. The input reflection (S11), output reflection (S22) and return loss (S12) are -10.65, -20.02 and -52.23 dB, respectively. The measured 3 dB bandwidth of 1.24 GHz has been achieved. The input sensitivity is -84 dBm exceeded the standards required by IEEE 802.16 has been observed.

Transformer models trained on long sequences often achieve higher accuracy than short sequences. Unfortunately, conventional transformers struggle with long sequence training due to the overwhelming computation and memory requirements. Existing methods for long sequence training offer limited speedup and memory reduction, and may compromise accuracy. This paper presents a novel and efficient distributed training method, the Long Short-Sequence Transformer (LSS Transformer), for training transformer with long sequences. It distributes a long sequence into segments among GPUs, with each GPU computing a partial self-attention for its segment. Then, it uses a fused communication and a novel double gradient averaging technique to avoid the need to aggregate partial self-attention and minimize communication overhead. We evaluated the performance between LSS Transformer and the state-of-the-art Nvidia sequence parallelism on a Wikipedia enwik8 dataset. Results show that our proposed method lead to 5.6x faster and 10.2x more memory-efficient implementation compared to state-of-the-art sequence parallelism on 144 Nvidia V100 GPUs. Moreover, our algorithm scales to an extreme sequence length of 50,112 at 3,456 GPUs, achieving 161% super-linear parallel efficiency and a throughput of 32 petaflops.

This comparative research study explores the efficacy of two parallel systems, Model A employing a hot standby configuration and Model B utilizing a cold standby setup, each comprising three units operating based on demand. The investigation focuses on evaluating the reliability and cost-effectiveness of these systems, employing metrics such as Mean Time to System Failure, availability at full and reduced capacity, repairer busy periods, downtime, and profit analysis using Semi-Markov and regenerative point techniques. Results reveal that Model B (cold standby) outperforms Model A (hot standby) across multiple parameters, including Mean Time to System Failure, availability, repairer busy periods, downtime, and profitability. Specifically, Model B demonstrates higher values for Mean Time to System Failure, Availability at full and reduced capacity, Busy period for repairmen, and Profit in Rs. Consequently, it is inferred that Model B proves to be more reliable and efficient than Model A. These findings underscore the potential advantages of employing cold standby configurations in similar machinery setups, offering insights to enhance system performance and minimize downtime, thus suggesting avenues for optimizing cold standby parallel systems based on the study's outcomes.

This article proposes a photovoltaic system of ultrathin silicon solar cell by using indoor lighting through enhanced shunt resistance, nanostructure of light-trapping, and tubular daylight system for powering the internet of things (IoT) devices. Simulation results show that, by increasing the shunt resistance from 100 Ω.cm2 to 104 Ω.cm2, the efficiency of indoor solar cell can be improved from less than 0.5% to be over 14%. Moreover, with the help of ultrathin wafer and nanostructure of light-trapping to improve the near-infrared light absorption and open circuit voltage, the efficiency of the indoor amorphous silicon (a-Si) heterojunction solar cell can be further improved to be 17.09%. The tubular daylight system is an excellent supplement to the light indoor intensity and thus can increase the power production.

Nowadays tidal current energy conversion system (TCECS) is being developed with a capacity of 100 kW for Indonesian waters. The design process is based on the results of field measurements, i.e., ocean currents, tides, ocean waves, and bathymetry. This paper aims to explain the experiences when collecting oceanography data in a potential site for TCECS. The survey method is that the equipment placed on the seabed will emit signals that can record flow and wave data according to the desired time and depth. The survey process, especially for the tidal current energy application, requires good preparation so as not to fail. The results of this paper explain the challenges and highlight the steps. These are technical, environmental, and survey permits. The technical aspects are tool stability, buoyancy effects, visualization tools with an underwater camera system, seawater brightness, and sedimentation. Environmental aspects are big waves, strong currents, and weather. The survey permit aspects are destruction and conservation area. Therefore, before the survey, safety procedures or documents must be made in the form of HIRA (Hazard Identification and Risk Analysis). The experiences of this survey are a novelty consideration for other surveyors in the tidal current energy aspect.

To analyze the impact of different objective functions and additive manufacturing (AM) constraints on structural topology optimization, it is necessary to perform an in-depth comparative study. This analysis should consider specific structural design factors, such as compliance, volume, or stress minimization, and assess their effects on the topology optimization for AM. In addition, the inclusion of AM constraints can have a significant influence on various aspects, including optimal part geometry, part volume, support structure volume, and structural performance. Thus, it is essential to investigate and compare these factors to determine the optimal part design for AM. This study focuses on comparing topology optimization results obtained using compliance, stress, or multi-objective minimization, with and without AM constraints. A comparative analysis was conducted in the study, utilizing three structural design examples: cantilever beam, bridge-shaped structure, and L-shaped beam...

Mjerni sustav sastoji se od mjerne strojne opreme s ugrađenom mjernom jedinicom s pripadajućim senzorskim sustavom za mjerenje vlačnih i/ili longitudinalnih kompresijskih opterećenja i njihovih mehaničkih deformacija te pripadajućeg softvera za slobodno programiranje i kontrolu procesa mjerenja, automatsko prikupljanje podataka, vrednovanje i prezentaciju tih

Sentiment analysis is a useful tool in several social and business contexts. Aspect sentiment classification is a subtask in sentiment analysis that gives information about features or aspects of people, entities, products, or services present in reviews. Different deep learning models that have been proposed to solve aspect sentiment classification focus on a specific domain such as restaurant, hotel, or laptop reviews. However, there are few proposals for creating a single model with high performance in multiple domains. The continual learning approach with neural networks has been used to solve aspect classification in multiple domains. However, avoiding low, aspect classification performance in continual learning is challenging. As a consequence, potential neural network weight shifts in the learning process in different domains or datasets. In this paper, a novel aspect sentiment classification approach is proposed. Our approach combines a transformer deep learning technique with a continual learning algorithm in different domains. The input layer used is the pretrained model Bidirectional Encoder Representations from Transformers. The experiments show the efficacy of our proposal with 78 % F1-macro. Our results improve other approaches from the state-of-the-art.

DOI: 10.35629/5252-0401779789 Impact Factor value 7.429 | ISO 9001: 2008 Certified Journal Page 779 Hydrological Simulation of a Pancheshwer Basin using SWAT CUP Model Harish Kumar Dwivedi, Hardeep Maurya, Keshav Kumar Sharma, Mukesh Kumar, Shakti Suryavanshi 1 Research Scholar, Department of civil engineering, Sam Higginbottom University of Agriculture, Technology & Sciences, Prayagraj, Uttar Pradesh 2 Research Scholar, Department of civil engineering, Indian Institute of Technology Jammu, Jammu & Kashmir 3 Assistant Professor, Department of Civil Engineering, NIT Jamshedpur, Jharkhand 4 Assistant Professor, Centre for Geospatial Technologies, Sam Higginbottom University of Agriculture, Technology & Sciences, Prayagraj, Uttar Pradesh 1 Assistant Professor, Department of Civil Engineering, Sam Higginbottom University of Agriculture, Technology & Sciences, Prayagraj, Uttar Pradesh *Corresponding Author: Harish Kumar Dwivedi

The need to deal with variability in wind power output is one of the greatest challenges connected with adopting a considerable amount of wind power into power grids. Power system operators need to acquire more information on this variability, which can be utilized in the mitigation of high ramping events, especially when these events synchronize with a large error in the prediction, ensuring flexibility and reliability in the power system besides the economic considerations. The paper analyses short-term variability in output power using actual data obtained from aggregated wind farms from 2015 to 2020, where power ramping characteristics are described using a variety of measurements. The use of the standard deviation of short-term wind power variation as a reserve measure will be investigated in detail since there is no consensus about the ideal confidence level value as a multiplier of σ, which ranges from 3 to 6 times σ. The paper addresses how large this confidence level should be, as well as developing a data-driven approach for estimating this reserve with increasing wind shares and evaluating the proper distribution of short-term wind variation. The results illustrate that the stochastic variations in wind power can retain many of their characteristics from year to year, even when the share of wind capacity is raised.

This paper presents a switched capacitor voltage multiplier with resonant-type current between capacitors; these current waveforms are achieved by designing a resonant topology combined with a safe switching strategy. Moreover, the proposed converter provides interleaving capability, soft switching, modular structure and a reduced number of components. These features yield a low cost converter with high voltage gain scalability, reduced input current ripple and limited peak currents between capacitors. Experimental results that corroborate the advantages of the proposed topology are presented.