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2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawideband (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capicitance (LC) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these LC circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, n, minimizing the NE, The eScholarship provides open access, scholarly publishing services to the University of California and delivers a dynamic research platform to scholars worldwide. designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18-mu m CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.
2013 IEEE International Wireless Symposium (IWS), 2013
A low-power, highly linear CMOS doublebalanced mixer for UWB applications is presented. The mixer is designed based on well-known folded architecture and also benefits from DC isolation of RF (Radio Frequency) and LO (Local Oscillator) stages. Stacked NMOS-PMOS g m-boosting topology is used in the design of RF stage. To achieve very low power consumption, this stage is biased in sub-threshold region. Also an ultra-wideband active balun is designed and fabricated to generate differential inputs. The balun is separately characterized and its performance is reported both separately and together with the mixer. The design is implemented using 130 nm CMOS process and is operational from 3.1 to 10.6 GHz. The measured maximum conversion gain shows high value of 14.9 dB for the mixer core. Also, the measured double sideband noise figure has a minimum value of 7.8 dB for the mixer core and 12.9 dB when balun is added. Input (RF and LO) port matching is achieved with reflection of more than 10 dB for the entire band. Furthermore, port-toport isolation is measured that shows excellent isolation between ports. Measured IIP3 as a good indication of linearity performance is also reported and shows excellent linearity that is a result of techniques used in the design. Finally the mixer core area is measured to be 0.056 mm 2 with power dissipation of 623 µW from a 1.2 V supply.
Journal of Electron Devices, 2012
It is also essential to realize the mixer with reasonable linearity, so that the impact of mixing with the external interferers can be minimized. For the mixer circuit, IIP3, IIP2 are the important design parameters to measure the linearity besides the conversion gain and noise figure [3]. ...
This paper presents the design of a 3.1-10.6 GHz down-conversion mixer for ultra-wideband (UWB) system with 0.18 μm SMIC CMOS technology. The mixer with an active balun was fabricated in the 0.18 μm IP6M standard CMOS process. The broadband mixer with an active balun achieve a conversion gain of 16 ± 0.1 dB and 7.6 -11.8 dB on a double-sideband (DSB) noise figure. It also achieved an input thirdorder intercept point (IIP3) of -1.89 to -1.8 dBm. The mixer with active balun consumed 17.3 mW from a 1.2 V supply. This circuit did not match S11,or S33 to save chip area.
Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology, 2011
This letter presents a low power, low noise CMOS double-balanced direct conversion mixer for ultra-wideband systems. The mixer is a critical block to perform the frequency translation in ultra-wideband systems. The proposed mixer employs three techniques: the sub threshold operation of transistors for the radio frequency stage reduces current dissipation in the overall mixer, a local oscillation (LO) stage using an inverter lowers the required LO amplitude, and an active load improves conversion gain. The mixer was implemented using a 0.18 um CMOS process and was operated from 3.1 to 5.7 GHz. The measured results show a high conversion gain up to 22.0 dB and a maximum noise figure of 8.0 dB.In addition and a power dissipation of 5.535 mW from a 1.8 V supply.
This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capicitance ( ) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, , minimizing the NF. The designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18m CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.
IEEE Transactions on Microwave Theory and Techniques, 2000
A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-m CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP 3 and IP 1 dB , and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9 1.5 dB, input 1-dB compression point (IP 1 dB) of 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP 3) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 0.57 mm 2 .
Microelectronics, Electromagnetics and Telecommunications, Volume 372, Lecture Notes in Electrical Engineering, pp 485-495, 2015
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
2012 6th International Symposium on Telecommunications, IST 2012, 2012
This paper presents a low-voltage low-power downconversion mixer for 0.5~11 GHz, MB-OFDM UWB applications. The mixer operation is simulated in TSMC 0.18-µm CMOS process. To decrease supply voltage and power consumption, the RF and LO stages are merged together into one stage, so that the RF and LO signals apply to the source and gate of the devices, respectively while the IF output signals is produced from the drain. The mixer features a maximum conversion gain of 7.8 dB in 5.8 GHz, a low dc power consumption of 1.3mW, a DSB noise figure of 16.4 dB, an IP 1dB of-10 dBm and an input IP3 of 4dBm. The 3-dB RF bandwidth is from 0.5 to 11 GHz with an IF frequency of 100 MHz. The mixer draws 1.3 mA from a power supply of 1 V leading to a low-power operation.
arXiv (Cornell University), 2012
The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.
Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, 2010
This paper presents a low power, UWB up-conversion mixer, designed on CMOS 0.13 µm technology. This circuit is based on a double balanced Gilbert topology, which uses a feedback loop in its transconductance stage; in order to match the IF input impedance over a 10-510 MHz frequency range. This mixer exhibits a 0 dB conversion gain, a 7 dB noise factor, a DC power in the range of 4.2 mW and can output an RF signal over the 6-8.5 GHz frequency range.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2008
To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13-m CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3-to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies. Index Terms-CMOS integrated circuits, distributed amplifiers (DAs), noise, ultra-wide-band (UWB). I. INTRODUCTION U LTRA WIDE-BAND (UWB) is a recently licensed shortrange wireless technology capable of transferring digital data at high data rates at low powers. UWB systems transmit and receive signals that are dense in time domain and spread in frequency domain, instead of conventional sinusoidal signals widely used in narrowband wireless systems. According to FCC regulations [1], the licensed frequency band of UWB systems is from 3.1 to 10.6 GHz where the transmitted signal power must be limited to dBm Hz to avoid interference with other narrowband wireless systems. At the receiver end, a wideband LNA is essential immediately after the antenna to increase the very limited power of the received UWB signal as shown in Fig. 1. A typical power gain larger than 10 dB and a very good noise performance is required, while the input return loss of the amplifier must remain below dB. Most of the previous attempts for design of UWB low-noise amplifiers (LNAs) [2]-[4] were based on the bandwidth extension of the popular narrowband inductively source-degenerated amplifier [5]. In this paper, we propose an alternative design approach based on a modified distributed amplification method. Distributed amplification technique is selected because of its potential of providing a flat
IEICE Transactions on Electronics, 2005
This paper represents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.
A new fully differential ultra low-voltage, ultra low-power down-converter mixer for ultra wideband application is presented in this paper. This mixer is designed using four-terminal MOS transistors. The radio frequency is applied to source and local-oscillator signal is applied to the gate with body of devices simultaneously. A DTMOS common source amplifier is employed increasing conversion gain. The proposed circuit is designed and simulated in the TSMC 0.18μm CMOS process. The simulation results show that the proposed mixer has a peak conversion gain of 12.3dB with 3dB RF frequency bandwidth from 2GHz to 10.5GHz with a fixed IF frequency of 100MHz. The third-order intermodulation-intercept point (IIP3) varies from -5.2dBm to -7.3dBm between 2-10.5GHz. The proposed mixer consumes only 1.28mW power with 0.5V supply voltage.
2013
In this paper, a CMOS down-conversion mixer for UWB applications is presented. The mixer circuit is designed using a VIS 0.25μm RF CMOS technology, working at the 0.9GHz-10.6GHz frequency range; it will be used in applications such as IEEE WiFi, GSM and WiMAX. The core of the mixer has been designed based on double-balanced cell architecture, and uses the current bleeding method to increase the linearity and improve the conversion gain. We put a resistor on the drain of the MOS between two RF inputs, which will improve the flatness of conversion gain. Regarding the arrangement of the mixer, the RF frequency is set at 0.9GHz-10.6GHz, the LO frequency 0.8GHz-10.5GHz and the IF of 100MHz. The simulated conversion gain of the mixer is 7± 1dB. The 1dB compression point is higher than-11dBm at high frequency and-9dBm at low frequency. The RF input return loss is well below-11dB, and the LO input return loss is below-10dB. The noise figure is 12.93dB while IF is 100MHz, and the mixer core dissipates 9.8mW under a 1.8 V supply.
2009
This work presents low noise amplifier (LNA) and mixer with an active Balun for 8-9 GHz Ultra-wideband (UWB) system. The LNA uses the self-biased method to eliminate the Miller effect and no extra bias circuit is needed. The mixer uses the Gilbert cell topology to enhance the isolation performance. The proposed mixer which uses an active balun at the input port reveals a larger conversion gain than by using a micromixer topology which varies the signals at the transconductance stage. The LNA and mixer are also integrated together on a printed circuit board (PCB). Fabricated in CMOS 0.18μm technology, the conversion gain of LNA and mixer is 17.4dB when one IF port is terminated to 50Ω. The total power consumption is 41.4dBm, the LO-to-IF isolation is 35.6dB, and the 1-dB compression point is -20dBm.
IEEE Journal of Solid-State Circuits, 2006
A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31 GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15 dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15 dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.
2017
This paper presents an important review on mixer and balun designs for several UWB (ultra-wideband) applications that generally operate in frequencies ranging from 3.1 to 10.6 GHz. This paper begins with an introduction of mixer and balun terminologies, followed by discussion and comparison of several types of mixer designs and their performance on conversion gain, noise figure, third-order intercept points input, and port-to-port isolation. Balun plays an important role in RF mixer designs as it converts the single-ended signal coming from LNA into a differential signal that suitable for mixer input terminal. Hence, baluns provide impedance transformation and matching network for structures transition in mixer designs. The previous studies are reviewed and compared in order to gain a better understanding in RF mixers. An alternative design of balun can be suggested to be utilized in mixer designs to produce overall good performance for multi- function operation in UWB applications.
2015
A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.
International Journal of Computer Science Issues, 2012
The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.
TELKOMNIKA Telecommunication Computing Electronics and Control, 2019
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of-20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of-8 to-16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer's ports.
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