Design and analysis of a distributed regenerative frequency divider using distributed mixer

Microwave and Optical Technology Letters, 2009

IEEE Microwave and Wireless Components Letters, 2000

This paper presents a 0.13 µm CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of its phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19 GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15 GHz, 31% locking range. The divider dissipates 3 mA from 1.2 V power supply.

IJIRST, 2014

A low power 1MHz Full programmable frequency divider in 45-nm CMOS process is presented in this paper. The divide ratio can be varied from 2400 to 2431 in a step size of 1.The divider consists of a divide-by-2 circuit, divide-by-2/3 prescaler, divide-by-32/33 prescaler, a programmable pulse-swallow counter. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 2.46GHz-2.541GHz. Measured results show that programmable divider consuming only 613.39 µW at 1V power supply. The programmable frequency divider is design and simulated on Tanner EDA Tool using 45nm CMOS process technology with supply voltage 1 V.

International Journal of Computer Science Issues, 2012

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

IEEE Journal of Solid-State Circuits, 1995

This paper describes an analog frequency divider HEMT HEMT hplifier Low pass filter Mixer by two working in the millimeter wave frequency range around 60 GHz. This circuit is analyzed with a new method that allows to determine the steady-state regime of any synchronized circuits with standard CAD commercial software. The method proposed relies upon the concept of open loop systems and is applicable to any feedback transistors circuits. The designed circuit was processed using a standard 0.25-pm HEMT technology. Four (2 2) N [ z) transistors were used for realizing the frequency division function as well as the input and output amplification. More than 10% Fo/2 Feedback filter frequency bandwidth and gain Fig. 1. Closed loop diagram of a regenerative FET frequency divider. was obtained using input and output buffers. Measured results were found in good agreement with simulated ones.

2003

A 2:1 static frequency divider was fabricated in a 0.12-μm SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005

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IEEE Microwave and Wireless Components Letters, 2005

This paper presents a 0.13 µm CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of its phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19 GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15 GHz, 31% locking range. The divider dissipates 3 mA from 1.2 V power supply.

IET Circuits, Devices & Systems, 2007

A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-mm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.

Microwave and Optical Technology Letters, 2008

This study proposes a new low-voltage divide-by-3 CMOS injection locked frequency divider (ILFD) fabricated in a 0.18-m CMOS process and describes the operation principle of the ILFD. The ILFD circuit is realized with a CMOS dynamic threshold voltage LCtank voltage-controlled-oscillator (VCO) with two injection MOSFETs. The self-oscillating VCO is injection-locked by third-harmonic input to obtain the division order of three. Measurement results show that at the supply voltage of 0.36 V, the free-running frequency is from 1.015 to 1.093 GHz. At the incident power of Ϫ10 dBm, the locking range is from the incident frequency 3.01 to 3.33 GHz. This is the lowest voltage ILFD ever reported in literatures.