CMOS wideband analogue delay stage

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2013 IEEE International Conference on Electronics, Computing and Communication Technologies, 2013

In this paper a second order all pass filter (APF) is designed and analyzed for its potential application for wideband chirp waveform generation. The group delay of a single stage APF varies with frequency within a narrow band and remains flat elsewhere. Furthermore, it has been found that the component values have a great role in the group delay response of the APF. A two stage cascaded second order APF is adopted to enhance the group delay over a wider band. Genetic algorithm is used to optimize the design parameters of the individual APF stages to obtain a smooth and monotonically increasing group delay response while ensuring good input return loss characteristics. This design approach can be used for generating wideband chirp waveforms that have potential applications in radar, sonar and imaging, delivering improved range resolution.

— This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of ±25 ps using the standard 0.18 µm CMOS technology. Weak Capacitive-Resistive shunt feedback technique is implemented across the input stage for wideband input matching. Series peaking with output resistive termination are adopted for group delay variations optimization. This UWB LNA has a measured 1dB compression point (P1dB) and an input third-order inter-modulation point (IIP3) of-7.0 dBm and 2.5 dBm respectively at 5.5 GHz. The implemented UWB LNA chip area is only 560 µm x 590 µm. Keywords — CMOS, group delay, low noise amplifier (LNA), ultra-wideband (UWB), current reuse, noise figure (NF), capacitive-resistive feedback, series peaking

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

This paper describes the implementation of delay element using C 4 band-pass filter for subband analog tapped-delay adaptive filter, where implementation of larger group delay is required. Most analog delay elements have been implemented with low-pass or all-pass filters. While they can easily achieve constant group delay within pass band, maximum group delay is severely restricted by the corner frequency because group delay is inversely proportional to the corner frequency. In this paper, we implemented a delay element with a Capacitively-Coupled Current Conveyer (C 4) band-pass filter to produce larger group delay required for analog subband adaptive filter. Experimental results from circuits fabricated in 0.5µm CMOS technology through MOSIS are also presented.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a Σ∆ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.

Analog Integrated Circuits and Signal Processing, 2019

The strategy of improving the group delay in analog filters through the modification of conventional characteristic polynomials is a concept reported in advanced filter design literature. However, at present, this idea has only been approached from a theoretical perspective, validated by numerical or electrical simulations but not experimentally verified. This paper is precisely devoted to exploring the viability of physically realizing this idea. Because most of the references that deal with this topic consider the case of Chebyshev filters, this type of filters is also considered in our experimental validation. In our proposal, a synthesis based on FDNR topology (frequency-dependent negative resistor) is preferred over other circuit design strategies due to its low sensitivity. In order to verify the physical realization capability of this type of filter, the experimental results of a fifth-order Chebyshev filter implemented by using commercially available JFET opamps TL082 are reported. In this case study, the frequency (magnitude and group delay) and time (step) responses of the conventional filter are contrasted with those of the modified filter, demonstrating that the experimental results accord with the theoretical background.

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007

This paper presents a behavioral model of a delaylocked loop (DLL) used to generate the timing signals in an integrated ultra wide-band (UWB) impulse radio (IR) system. The requirements of these timing signals in the context of UWB-IR systems are reviewed. The behavioral model includes a modeling of the various noise sources in the DLL that produce output jitter. The model is used to find the optimum loop filter capacitor value that minimizes output jitter. The accuracy of the behavioral model is validated by comparing the system level simulation results with transistor level simulations of the whole DLL.

IEEE Journal of Solid-State Circuits, 2007

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 m CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported. Index Terms-Beamforming, CMOS integrated circuit, pathsharing true time delay architecture, phased array, radar, timed array, true time delay (TTD) circuit, ultra-wideband (UWB).

— This paper presents a direct design of Infinite Impulse Response filters (IIR filters) which minimizes group delay without changing the magnitude response of filters. In this paper Butterworth and Chebyshev1 lowpass filters are designed by using allpass filters. The design specifications are passband and stopband frequencies and passband ripple and stopband attenuation. In this paper MATLAB programming is used for implementation of proposed algorithm. Experimental results show that the proposed method can effectively optimize the group delay of the designed Butterworth and chebyshev1 low pass filters.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005

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Microwave and Optical Technology Letters, 2009

This article presents a novel dual-band HTS filter using open-loop stepped impedance resonators (SIRs) and /4 spiral open stubs. The center frequencies of the two passbands are determined by the structure of the SIRs. By introducing the /4 spiral open stubs, the external quality factor of the second passband can be tuned independently without influence on that of the first one. The measured results of the filter at 77 K are in good agreement with the simulated ones.

IEEE Journal of Solid-state Circuits, 2007

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 m CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate. . The work of M. Verhelst was supported by a fellowship from the Fund for Scientific Research-Flanders (Belgium) (FWO-Vlaanderen) J. Ryckaert and P. Wambacq are with IMEC, 3001 Leuven Belgium, and also with Vrije Universiteit Brussel, 1050 Elsene, Belgium (e-mail: ryckj@imec.be).

We present a Programmable Delay Control (PDC) for UWB Timed Array Radar Application, working with pulses in the GHz region, which requires a precise control of delays in the order of picoseconds. The major component of the PDC consists of a channel formed by two static inverters connected in series. Between the internal transition line (Vlinha) and the ground line (Vss), a digital variable capacitor is used to control the time of transitions (low-to-high and high-to-low) through their different times of charging and discharging. The circuits are designed using the integrated Spice environment with MicroWind 3 and LTSpice 4 VLSI Full custom project tools with the IBM SiGe 0.18 um process foundry. The Spice simulations showed a controllable delay time between 0 and 97ps, which, in the EM tests with CST Microwave Studio 2011, resulted in a controlled beam with center frequency of 4GHz, angular width of 27 ° and variable deflection between 12 º and -13 º, with a 8.3dB directivity and si...

International Journal of Reconfigurable and Embedded Systems (IJRES), 2025

Ultra-wide band (UWB) is a wireless technology deployed for transmitting data at high rates over short distances. Similar to Wi-Fi and Bluetooth, UWB is a radio frequency (RF) technology that operates via radio waves. To remove minor noise and glitches, low noise amplifier (LNA) is required because it amplifies weak signals without significantly adding noise. However, UWB has multiple frequencies that require coefficient change due to frequency variations. When low-pass filter (LPF) is employed to solve this, updates are necessary to manage delay and power because the LPF feedback is connected to LNA to increase delay and power consumption. In this research, LNA with a pre-distortion architecture is proposed to remove minor noises and small glitches. It is processed by using pre-distortion as an active component which reduces delay and power consumption in UWB. The pre-distortion process operates in the subthreshold voltage range by providing a transistor to each frequency as input, inturn effectively reducing the noise. The proposed LNA with pre-distortion architecture is developed on 180-nm complementary metal-oxide semiconductor (CMOS) technology using Cadense ASIC tool. The proposed architecture achieves a noise figure (NF) of 2.16 dB and less power consumption of 43.06×10-6 W when compared to the existing techniques namely, cascade amplifiers, W-band LNA, reflectionless receiver (RX), and broadband RF receiver front-end circuits.