CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing

IEEE Sensors Journal, 2014

This paper presents a low power neural signal amplifier with tunable cutoff frequencies. The presented compact amplifier, which is used for sensing various types of neural signals, reduces the size and the power consumption of the whole circuit. The distinguishing features of this solution are the large time constant, linearity, and small achievable area, which are realized with a configurable series of pseudo resistances. The proof of concept has been manufactured on TSMC 90 nm technology. Index Terms-Brain-computer interface, large time constant, neuro-amplifier, pseudo-resistor, LFP, fully differential OTA, common-mode feedback. I. INTRODUCTION T HE BIOMEDICAL field is one of the most dynamically developing research area in the analog IC design, specially the low-power implementations for implantable neural interfaces. Some of the examination procedure needs a longerterm recording as it is available with fMRI and better spatial resolution than using EEG technique [1], [2]. Even though in our experiment the portability of the measuring instrument is not an important issue, in principle, it is a relevant question to ensure the freedom of movement of the test subject. Our interest concerns mostly the implantable cortical micro sensor arrays, which causes minimal structural damages in the analyzed region. From the engineer's aspect, measuring the Manuscript

Proc. IEEE Custom …, 2010

We present a 6.4 µW electrocorticography (ECoG)/electroencephalography (EEG) processing integrated circuit (EPIC) with 0.4 µVrms noise floor intended for emerging brain-computer interface (BCI) applications. This chip conditions the signal and simultaneously extracts energy in four fully-programmable frequency bands. Functionality is demonstrated by tuning the four bands to important frequency bands used by ECoG/EEG applications: α (8-12Hz), β (18-26Hz), low-γ (30-50Hz) and γ (70-100Hz). Measured results from in-vivo ECoG recording from the primary motor cortex of an awake monkey are presented.

IEEE Access

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a −3dB bandwidth in the range 0.1-212 Hz. Moreover, the amplifier is designed in 0.18-µm CMOS process and the chip area of the proposed circuit with pads is 450 × 450 µm 2. The adjustable LPF has a 100 Hz cutoff frequency. The proposed circuit has an input-referred noise of 0.7 µVrms, (0.1 ∼ 100Hz) and a power consumption of 380 nW at 1 V supply. INDEX TERMS Fully recycling folded cascode amplifier, chopper-stabilized technique, EEG, Gm-C filter, low-noise design.

Electronics, 2019

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .

Bioengineered and Bioinspired Systems III, 2007

Electroencephalograph (EEG) recording systems offer a versatile, non-invasive window on the brain's spatiotemporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 µW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours. Coupling between the bit-serial output and the highly sensitive analog input due to dense integration of analog and digital functions on the circuit board results in a deterministic noise component in the output, larger than the intrinsic sensor and circuit noise. With software correction of this noise contribution, the system achieves an input-referred noise of 0.277 µVrms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. A chain of seven nodes using EEG dry electrodes created in micro-electrical-mechanical system (MEMS) technology is demonstrated in a real-world setting.

2018

In an endless effort for developing new assistive technologies to treat neural disorders, neural interface technology has seen tremendous progress. For designing analog front-end in neural interface system, the Low Noise Amplifier (LNA) design for low frequency neural signals is still a challenging task. Specific design requirements for neural LNA require a decent understanding of various topologies used for its implementation. This paper discusses standard design parameters and their desirable values for LNA design. A comparison of System-level architecture: Open loop and Closed-Loop topologies are also presented. A summary of various strategies is explained based on the improvement in design for low power, low noise and area. The current mirror OTA with capacitive feedback topology is simulated using 0.18μm technology node using BSIM3V3 MOS Transistor Model from Cadence. Using gm/Id methodology for selection the operating point the transistors, a low noise and low power amplifier ...

Recording neural signal from a living human body is a complex task and it is an important research issues for neuroscientists and researchers in biomedical engineering. The major issue to overcome in the design of a system that is aimed at being implant into the human body is having a low power consumption, low noise circuit and small dimension to minimize tissue damage. In this paper, specific issues of the most important part of such a neural acquisition system are presented; in particular, the design of a low-power amplifier, for a fully implantable neural recording system, is described. The amplifier uses a differential pair as input stage. Given that neural amplifiers must include differential input pair to achieve a high common-mode ratio rejection (CM RR). The amplifier has been designed in the AMS 0.35 µm standard CMOS process. The amplifier current consumption is 4.61 µA at ±1V supply, which gives a power consumption of 9.22 µW. The low cutoff frequency is adjustable from 21 Hz to 100 Hz, with four tunable gains of 43.6 dB, 48 dB, 50 dB and 52.8 dB. The upper cutoff frequency is about 7.6 kHz. The CM RR is 113 dB and the power supply ratio rejection is P SRR > 73dB. The input referred noise is 14.8 µV rms over 100 ∼ 10 kHz. The amplifier gives an input DC offset of 196 µV.

Electronics, 2022

Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life of patients with brain diseases, and a great deal of effort has been focused on the development of implantable devices. This paper presents a low-noise amplifier (LNA) for the acquisition of biopotentials on DBS. This electronic module was designed in a low-voltage/low-power CMOS process, targeting implantable applications. The measurement results showed a gain of 38.6 dB and a −3 dB bandwidth of 2.3 kHz. The measurements also showed a power consumption of 2.8 μW. Simulations showed an input-referred noise of 6.2 μVRMS. The LNA occupies a microdevice area of 122 μm × 283 μm, supporting its application in implanted systems.

2007

Electroencephalograph (EEG) recording systems offer a versatile, non-invasive window on the brain's spatiotemporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 µW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours.

Journal of Low Power Electronics and Applications, 2013

Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA) with the capability of recording local field potentials (LFP) and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm 2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µV RMS. Ability of the NA to perform spike recording

This paper proposes a high gain, low power instrumentation amplifier (IA) for EEG signal processing. A three opamp instrumentation amplifier has been designed by using sub-threshold three-stage op-amps with PMOS input. NMOS transistors operating in the triode region have been used to replace the passive resistors of IA. This eliminates the problems of mismatch, temperature dependency and large area consumption, at the same time taking advantage of the high CMRR and DC offset cancellation properties of conventional IA. A BGR circuitry with temperature coefficient of 420 ppm/oC is used to bias the opamp. The instrumentation amplifier is simulated in Cadence Virtuoso 180nm CMOS technology by using a supply voltage of IV. It achieves a Gain of 96.4dB, Bandwidth of 400 KHz, input-referred noise voltage of 610nV//"" Hz, CMRR in the range of 60dB and power consumption about 53.7/lW.

2007

Electroencephalograph (EEG) recording systems offer a versatile, non-invasive window on the brain's spatiotemporal activity for many neuroscience and clinical applications. Our research aims at improving the spatial resolution and mobility of EEG recording by reducing the form factor, power drain and signal fanout of the EEG acquisition node in a scalable sensor array architecture. We present such a node integrated onto a dimesized circuit board that contains a sensor's complete signal processing front-end, including amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. The circuit's low power consumption of 423 µW supports EEG systems with hundreds of electrodes to operate from small batteries for many hours.

Microelectronics Journal, 2021

A four-channel, power-efficient, low-noise neural recording analog front-end (AFE) integrated circuit (IC) comprised of a low-noise amplifier (LNA), a programmable gain amplifier (PGA), and buffers is presented. The proposed AC-coupled capacitive-feedback LNA utilizes the inverter-stacking technique for the core operational transconductance amplifier which achieves four-time reduction in noise at minimal power consumption. The proposed PGA provides additional gain with tunable filtering function where the high-pass cutoff and low-pass cutoff frequencies can be controlled to acquire action potential and local field potential signals either simultaneously or separately. The overall AFE IC has a programmable gain range from 45 dB to 63 dB and achieves integrated input-referred noise of 3.16 μV RMS within the 10 kHz bandwidth, leading to a noise efficiency factor of 2.04 and power efficiency factor of 4.16. The AFE IC is implemented using 180 nm CMOS process and consumes 2.82 μW per channel powered from the 1-V supply voltage.

Journal of Circuits, Systems and Computers

This paper presents a fully integrated front-end, low noise amplifier (LNA), dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input-referred noise of the LNA, without adding any additional power. The proposed technique implemented in 65[Formula: see text]nm CMOS technology achieves 30 dB closed-loop voltage gain, 0.05[Formula: see text]Hz lower cut-off frequency and 100 MHz 3-dB bandwidth. It operates at 1.2[Formula: see text]V power supply and draws 1[Formula: see text][Formula: see text]A static current. The prototype described in this paper occupies 3300[Formula: see text][Formula: see ...

Journal of Neural Engineering, 2009

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.