Characterization of polycrystalline silicon thin films fabricated by rapid joule heating method

Journal of Electronic Materials, 1999

We report n-and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO 2 intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm 2 Vs and 1.8 V for n-channel TFTs, and 270 cm 2 Vs and 2.8 V for p-channel TFTs, respectively.

Microelectronics Reliability, 2007

The thermally activated mechanisms that determine the electrical properties of polycrystalline silicon thin film transistors have been investigated. The study employed devices fabricated on long grains and different thickness polycrystalline films, which were obtained by excimer laser annealing crystallization. The transfer and the transient characteristics have been recorded and analysed in the linear operation regime. The temperature dependence of basic parameters such as leakage current, subthreshold swing and drain current overshoot transient amplitude was found to stem from the same thermally activated carriers generation mechanism. The dependence of thermally activated mechanisms on the film thickness suggests that the device operation is strongly related to polycrystalline material properties.

Current Applied Physics, 2013

The source and drain regions were formed successfully by dopant induced crystallization method for top gate poly silicon thin film transistors. It was found that the resistance of source and drain varies with respect to dopant concentration and the grain boundary influence on resistance at different doses was intensively studied in this work. In the present study, boron was doped by ion mass doping (IMD) and PECVD and the resistance of 230 U was the doping condition of 2 keV 1 min and 17 keV 10 min in ion mass doping method. Thin film transistor by DIC exhibited a field effect mobility of 56 cm 2 /V s, leakage current of 4.1 Â 10 À11 A, slope of 0.84 V/dec, I on of 2.7 Â 10 À4 A, Vth of À6.5 V at V d ¼ 10 V In crystallization of in situ boron doped a-Si, 80 U in resistance was obtained at 1000 A. N type poly Si of 1000 A has 270 U in in-situ doping method. In-situ doped a-Si deposited by PECVD was further doped by using IMD. And the resistance was lowered by 10e20 U. Bottom gate thin film transistors fabricated by metal induced lateral crystallization (MILC) exhibits a field effect mobility of 26 cm 2 /V s, leakage current of 1.34 Â 10 À10 A, slope of 0.7 V/dec, I on of 1.02 Â 10 À4 A, Vth of 4.5 V at V d ¼ 10 V.

IEEE Transactions on Electron Devices, 1996

The characteristics of polycrystalline silicon thin-film transistors (TFT's), fabricated on films deposited in an LPCVD system using disilane, were investigated as a function of grain size. The grain size and its statistical distribution were correlated with processing conditions; optimum conditions to maximize grain size for device applications were determined. The dependence of the ON current and the OFF (leakage) current of polysilicon TFT's, as well as of their statistical distributions, on the grain size, the gate dielectric processing temperature, the channel length, and the device structure are reported and discussed. Larger grain size polycrystalline silicon films were found to yield devices with higher mobilities and lower leakage currents. TFT's, fabricated in polysilicon films with average grain sizes of 1.8 p m with thermally grown silicon dioxide as gate dielectric, had ON/OFF current ratio well above lo', average effective mobility value of 170 cm2/ V.s and subthreshold slope of 0.3 V/dec.

MRS Proceedings, 2000

Direct deposition of polycrystalline silicon (poly-Si) thin films by the Hot Wire CVD method has been used for the first time for the fabrication of poly-Si top gate Thin Film Transistors (TFTs). The TFTs have a high electron mobility in saturation of up to 4 cm 2 V -1 s -1 as well as a remarkably large ON/OFF ratio of up to 6 x 10 5 .

Microelectronic Engineering, 2008

Polycrystalline silicon quality is a key issue parameter for the performance and reliability of thin film transistors. Therefore in the present work, the material related electrical properties of TFTs fabricated on films crystallized by two different SLS-ELA procedures, 1-shot/overlapped irradiated, yielding different film textures, are investigated. The study employed devices with channel alighted across different orientation on the film. The transfer characteristics have been recorded and analyzed in the linear operation regime and temperature range of 120-440 K. The temperature dependence of typical parameters such as the sub-threshold swing and the leakage current is determined by the thermal generation of carriers through bang gap states, thus this study could provide information on the nature of these states. Furthermore the temperature dependence of mobility is related to scattering processes. The results suggest that TFTs fabricated on overlapped irradiated crystallized films exhibit similar performance independent of the channel orientation, while the highest mobility overall is obtained in devices fabricated across the preferable direction of 1-shot irradiated crystallized films.

Journal of The Electrochemical Society, 2002

A modulated process ͑MP͒ for the fabrication of low temperature processed ͑LTP͒ polysilicon thin-film transistors ͑poly-Si TFTs͒ using fewer processing steps but resulting in improved performance is investigated in this study. The modulated process is characterized by combining the solid-phase crystallization ͑SPC͒ step and the implant annealing into a single annealing step processed after the source/drain implantation. This is to say that the processing step of SPC is omitted, such that the SPC and implant annealing are conducted simultaneously. In this way, the process time is substantially shortened and the device performance is significantly improved. The improvement of device performance is presumably attributed to the larger poly-Si grain in the channel region processed by the MP scheme. In addition, the MP samples have a better NH 3-plasma passivation efficiency than the conventional process ͑CP͒ samples; this also implies that the MP samples contain larger grains in the channel regions than the CP samples. The electrical stress-induced degradation of device characteristics for the NH 3-plasma passivated MP samples is attributed to the carrier-induced metastable defects in the channel region.

IEEE Electron Device Letters, 1999

Solid phase crystallization has the advantages of low cost and excellent uniformity but the crystallization temperature is too high to use glass as a substrate. Using microwave annealing, we crystallized a-Si films at 550 'C within 3 h, which is much shorter than the annealing time at 600 'C of furnace annealing. We fabricated TFTs with poly-Si films crystallized by microwave annealing at low temperature and obtained the characteristics slightly better than or at least comparable to the TFTs by furnace annealing in spite of smaller grain size. This may be due to the improvement of surface roughness of poly-Si film. The poly-Si TFTs with PECVD a-Si film showed better characteristics than the TFTs with LPCVD a-Si film because of larger grain size and smoother Si/SiO2 interface.

Journal of Non-Crystalline Solids, 2002

Hydrogenated nanocrystalline silicon (nc-Si:H) obtained by hot-wire chemical vapour deposition (HWCVD) at low substrate temperature (150°C) has been incorporated as the active layer in bottom-gate thin-film transistors (TFTs). These devices were electrically characterised by measuring in vacuum the output and transfer characteristics for different temperatures. The field-effect mobility showed a thermally activated behaviour which could be attributed to carrier trapping at the band tails, as in hydrogenated amorphous silicon (a-Si:H), and potential barriers for the electronic transport. Trapped charge at the interfaces of the columns, which are typical in nc-Si:H, would account for these barriers. By using the Levinson technique, the quality of the material at the column boundaries could be studied. Finally, these results were interpreted according to the particular microstructure of nc-Si:H. Ó

Thin Solid Films, 2003

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently in future high-resolution, high-performance flat panel display technology. However, it is very difficult to fabricate high performance poly-Si TFTs at temperatures lower than 300 8C and the substrate temperature of the process is limited to less than 600 8C on glass. This paper describes a high temperature process above 750 8C to obtain poly-Si films. Hydrogenated amorphous silicon (a-Si:H) layer was deposited on a flexible Mo metal substrate and crystallized by rapid thermal annealing for TFT application. The a-Si:H films were crystallized at various temperatures between 750 and 1050 8C. As annealing temperature was increased, the TFT exhibited increased transconductance (g) and reduced voltage between drain and source (V), the threshold voltage (V). m d s T The high temperature annealed poly-Si film illustrated field effect mobility higher than 67 cm yVs. We also investigated the types 2 and activation energies of grain boundary trap, which are the function of annealing temperature. The poly-Si TFT showed an improved I yI ratio of 10 , reduced gate threshold voltage, and an increased field effect mobility by three orders.