Capacitive coupling noise in high-speed VLSI circuits

2001

Abstract Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise.

Nuclear Instruments and Methods in Physics Research …, 1996

Despite extensive literature on the analysis of noise in electronic circuits [1–7], it is sometimes difficult to generate an understanding at a useful fundamental level. The plethora of symbols used for a variable in different analysis can also make it very difficult to keep track of the ...

1999

Abstract—As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraint...

2015

Crosstalk noises have been estimated both for RC and RLC interconnects, respectively, in deep submicron VLSI circuits. The 2π model approach has been employed. The victim line is considered as an RC or RLC line, and the aggressor line is placed near the victim line. The aggressor line is excited with a voltage pulse at the coupling location keeping the victim line quiet. Analytical expressions of the output crosstalk noise voltages have been derived, and then the values of the peak noise voltages have been calculated. Subsequently, simulation work by HSPICE has been performed. The result shows an output crosstalk peak noise estimation of 6.29% error on average and that of 5.77% error on average compared with HSPICE simulation both for 2π RC and RLC interconnects, respectively.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however, for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. Design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.

This paper presents an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires, using RC interconnect model in two situations: simple resistance as driver and short channel CMOS inverter as a driver. The salient features of our proposed models include minimization of computational overhead, elimination of adjustment step to predict the peak amplitude and pulse width of the noise waveform. Numerical calculations are compared with SPICE simulation and other metrics by plotting the noise voltage verses time. Based on our proposed models, we derive analytical delay models due to RC interconnect in each case. Finally we formulate energy dissipation of the RC coupled interconnects in both the cases using our proposed metrics. Experimental results indicate that our models are closely comparable with SPICE simulation, with an average estimation error of 3.366%.

arXiv (Cornell University), 2023

Model order reduction (MOR) is crucial for the design process of integrated circuits. Specifically, the vast amount of passive RLCk elements in electromagnetic models extracted from physical layouts exacerbates the extraction time, the storage requirements, and, most critically, the post-layout simulation time of the analyzed circuits. The MORCIC project aims to overcome this problem by proposing new MOR techniques that perform better than commercial tools. Experimental evaluation on several analog and mixed-signal circuits with millions of elements indicates that the proposed methods lead to ×5.5 smaller ROMs while maintaining similar accuracy compared to golden ROMs provided by ANSYS RaptorX™.

Applied Numerical Analysis & Computational Mathematics, 2004

In recent years, model order reduction scheme for reducing the dimension of linear systems has become very popular for computer aided design of the systems. In this paper, we analyze the existent methods of the model order reduction techniques used in Very Large Scale Integrated (VLSI) circuit interconnection modelling in terms of numerical stability, computational speed and accuracy.

2011

Ever since its beginnings in the 1950’s, the integrated circuit (IC) has profoundly changed our lives. The way we work, travel, communicate, or address medical problems today has been facilitated by advances in microelectronics, which permit more functionality to be built on the same silicon area, at decreasing cost. As the feature size of devices on a chip shrink and circuits operate at increasing frequencies, the electromagnetic coupling effects between different IC components can no longer be ignored. To understand their impact on chip performance, these so called parasitic effects must be simulated. Parasitic networks are often so large, that state of the art simulation tools are insufficient to handle them: the simulations are either too lengthy, or cannot be carried out at all. The mathematical reason behind this is that the underlying systems are too large to be solved with the numerical algorithms implemented in simulation software. Model order reduction (MOR) provides one a...

2001

This paper presents a much improved, highly accurate yet efficient crosstalk noise model, the 2-¢ model, and applies it to noiseconstrained interconnect optimizations. Compared with previous crosstalk noise models of similar complexity, our 2-¢ model takes into consideration many key parameters, such as coupling locations (near-driver or near-receiver), and the coarse distributed RC characteristics for victim net. Thus, it is very accurate (less than 6% error on average compared with HSPICE simulations). Moreover, our model provides simple closed-form expressions for both peak noise amplitude and noise width, so it is very useful for noise-aware layout optimizations. In particular, we demonstrate its effectiveness in two applications: (i) Optimization rule generation for noise reduction using various interconnect optimization techniques; (ii) Simultaneous wire spacing to multiple nets for noise constrained interconnect minimization.