Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk.

2008

Capacitive crosstalk noise can affect the delay of a switching signal or induce a glitch on a static signal causing timing violations or chip failure. Crosstalk noise depends on coupling parasitics, driver strength, signal timing characteristics, and signal transition patterns. Layout level crosstalk analysis techniques are generally pessimistic and computationally expensive for large designs due to lack of design flexibility at lower-levels of design hierarchy. The architectural decisions such as type of interconnect architecture, number of storage and execution units, network of communicating units, data bus width, etc., have a major impact on the quality of design attributes such as area, speed, power, and noise. To address all these concerns, we propose a high-level synthesis framework to optimize for worst-case crosstalk patterns on coupled nets, a floorplan driven high-level synthesis framework to minimize coupling capacitance, and an on-chip technique to dynamically detect an...

Proceedings of the 2nd WSEAS International …, 2008

In recent times, crosstalk noise is playing a vital role in the performance of VLSI circuits, due to miniaturization of the feature size. In this paper, we propose an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires, using RC ...

This paper presents an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires, using RC interconnect model in two situations: simple resistance as driver and short channel CMOS inverter as a driver. The salient features of our proposed models include minimization of computational overhead, elimination of adjustment step to predict the peak amplitude and pulse width of the noise waveform. Numerical calculations are compared with SPICE simulation and other metrics by plotting the noise voltage verses time. Based on our proposed models, we derive analytical delay models due to RC interconnect in each case. Finally we formulate energy dissipation of the RC coupled interconnects in both the cases using our proposed metrics. Experimental results indicate that our models are closely comparable with SPICE simulation, with an average estimation error of 3.366%.

IEEE Transactions on Electromagnetic Compatibility, 1992

This paper shows how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behaviors by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed and the influence of crosstalk on the behavior of basic functions such as logic gate, latch, RAM memory, and analog-to-digital converter are evaluated.

Microelectronics Journal, 2008

Crosstalk noise and delay uncertainty are two major problems in modern very large scale integration (VLSI) design. To overcome these difficulties, a new dielectric structure is proposed for integrated circuits, which is in contrast to the conventional Cu/low-K technology. Both structures are simulated employing a field solver and a time domain simulator. Using the new dielectric structure, near-and farend crosstalk noises are reduced 45.2% and 15% in the test dimensions, respectively. The proposed structure, called gradually low-K, exhibits negligible side-effects in terms of delay and power consumption. Therefore, it is shown that the gradually low-K structure is a relevant choice to overcome the crosstalk and delay uncertainty problems, especially in the global interconnects tier.

This paper presents a closed form crosstalk noise modelling for on-chip VLSI RC interconnects using 2π model. For low frequency of operation, the interconnect can be modelled as distributed RC segments with sufficient accuracy. This crosstalk noise modelling is carried out for the case when step input is applied to the aggressor which is adjacent to the victim net. The proposed model represents the noise voltage waveform. In this paper, the original 2π model is further simplified and the closed form formulae for noise pulse width and noise amplitude for RC interconnect have been derived. This model considers various parameters, such as coupling location (near driver and near receiver) and course distributed RC characteristics for victim net. The proposed crosstalk model results in an error of less than 6% when compared to that of the SPICE simulation.

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

Process variations have an enormous impact on the amount of crosstalk in the circuit. Aggravation in crosstalk may lead to erroneous behavior of the circuit resulting in reduced product yield. Products have failed to meet targeted frequencies because of crosstalk problems. Therefore, a circuit should be designed such that there is a safety margin from erroneous circuit operation. At the same time, the design should not be so conservative that chip area and performance fall behind operational objectives. Whereas the combination of process parameters that give rise to worst-case noise is context dependent, we show in this paper how to efficiently determine process corners that can be used to approximate the worst-case crosstalk pulse or delay at the crosstalk site. Our experimental results show the accuracy gain of our process corners compared to traditional techniques while maintaining efficiency.

2015

With advancements in VLSI fabrication technology, interconnecting wires are being placed in closer proximity while circuits are starting to operate at higher frequencies. Thus, reduction in crosstalk between interconnects becomes an important consideration for VLSI physical design. In this paper, we have reviewed the effects and impact that crosstalk has on the performance and reliability of VLSI circuits and systems. We have also presented a concise but informative review on the various methods that researchers worldwide are implementing for a priori crosstalk avoidance or a posteriori crosstalk minimization in VLSI systems from the point of view of fabrication over the past few decades.

As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on-chip timing and even functionality. A method is presented to analyze crosstalk while taking into account timing relationship and timing criticality between coupling wires. The method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations. Based on these wire characteristics, a pattern driven routing tool imbeds the crosstalk critical nets in non-adjacent wiring tracks for crosstalk avoidance. The pattern driven routing capability may also be used for rerouting crosstalk critical nets of an already existing routing for crosstalk reduction. The crosstalk analysis and the routing tool described in this paper were used in three generations of VLSI processor chip designs for IBM's S/390 computers, always resulting in crosstalk-resistant hardware.