Analysis and optimization of ground bounce in digital CMOS circuits

International Journal of Information and Electronics Engineering, 2013

As technology is continuously scaling down leakage current is increasing exponentially. Multi-Threshold CMOS technique is a well known way to reduce leakage current but it gives rise to a new problem i.e. ground bounce noise which reduces the reliability of the circuit and because of this circuit may incorrectly switch to the wrong value or may switch at the wrong time. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of noise-aware forward body biased multimode MTCMOS circuit techniques to deal with the ground bouncing noise is evaluated in this paper. An additional wait mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by 93.28% and standby leakage current is reduced by 23.94% as compared to standard trimode MTCMOS technique. To evaluate the significance of the proposed multimode Multi-Threshold CMOS technique, the simulation has been performed for 16-bit full adder circuit using BPTM 90nm standard CMOS technology at room temperature with supply voltage of 1V .

Sub-threshold leakage current is exponentially increased with the scaling down the technology in CMOS circuits. MTCMOS is the method to reduce the leakage current but it arise a problem Ground bouncing noise which degrades the circuit reliability. Ground bouncing noise is important issue in MTCMOS circuits. It produced when circuit is transition from SLEEP to ACTIVE mode. This paper describes the various noise minimization MTCMOS techniques. The comparison of different techniques according to magnitude of Ground bouncing noise is tabulated. Dependency of Ground bouncing noise and power consumption on the various parameters like sleep transistor size, controlling transistor size, Temperature, supply voltage and threshold voltage is also characterized in this paper.

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

With technology scaling into the deep sub-micron regime, the power supply and ground noise, which is introduced by the simultaneous switching activity in digital circuits, becomes a challenge for SoC and Networks-on-Chip (NoC) design. In this paper, analytical expressions of the magnitude of ground bounce for different gate switching ratios are derived. It is shown that, by spreading the switching activity, asynchronous circuits design contributes to the ground bounce suppression in two aspects: (1) a significant decrease in the switching current strength and (2) a slight increase in the on-chip intrinsic decoupling capacitance. In order to minimize the switching ratio in large-scale digital VLSI systems, the globally asynchronous locally synchronous (GALS) design is exploited for coarse-grained scheduling and spreading the gate switching over different local clock domains. Important design guidelines, including the GALS system partitioning and local clock modulation, are discussed. As a practical example, a 64-point pipelined SYNC/GALS FFT processor was implemented using the IHP 130-nm CMOS process. The measurements on the packaged chip demonstrate that, compared with the synchronous mode, around 40% reduction in the magnitude of ground bounce is achieved in the GALS mode.

2015

Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE mode transition. FinFET based designs are compared with MOSFET based designs on basis of different parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software tool used for simulation and circuit design.

1996

Several techniques to reduce the ground bounce effect in CMOS chips are described. The effective width of the predrive and final driver of a CMOS output buffer is automatically adjusted to compensate for process, voltage, and temperature (PVT) variations. The slew rate of the predrive nodes is controlled by introducing a digitally weighted capacitance. Finally, a compensated active resistance is inserted into both the power and ground leads to further dampen the oscillations. These techniques allow the buffer to behave uniformly over the entire PVT range. Measurements of a 0.5-m CMOS test chip have demonstrated that these new buffers generate 2.52 less ground bounce when compared to conventional buffers. An external resistance is required to set a reference current.

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

Conventional power gating techniques for minimizing leakage currents introduce ground bounce noise during power mode transition. Here an analysis of ground bounce due to power mode transition in power gating structures is presented. An innovative power gating approach is proposed, which in addition to targeting maximum reduction of major leakage currents will provide a way to control ground bounce during power mode transition. The proposed power gating technique will have an additional intermediate HOLD mode along with conventional CUTOFF and RUN modes. Its stepwise turning on feature will provide higher reduction of the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999

The industry trend towards system-on-chip solutions continues to push the limits of mixed-signal design. Increasing the integration of analog and digital circuitry causes a struggle to maintain analog signal integrity. Digital switching noise coupling through the common substrate is both difficult to measure and difficult to control. This paper introduces and applies a practical first-order simulation methodology for performing a substrate noise analysis in a low resistive bulk process. Although this subject has been analyzed in numerous journal articles, few have applied their analysis method to a whole-chip design. This SPICE model will allow mixed-signal designers to determine design variables that will minimize substrate noise. This work elaborates on key aspects of substrate noise that available references do not handle adequately including: sources of substrate noise, determination of power rail and bulk resonance frequencies, and alternatives for bulk biasing. The new model is used to analyze Motorola's 56824, the latest low cost 16 bit DSP design. The analysis includes the determination of: 1) the on-chip bus and I/O bus noise coupled to the substrate, 2) the dominant resonant frequencies in the chip, and 3) the best bulk biasing alternative.

… on Electronic System …, 2010

In nanometer regime, ground bounce noise and noise immunity are becoming important metric of comparable importance to the leakage current and active power for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell is proposed for mobile applications with low ground bounce noise. A novel approach has been introduced with stacking power gating technique for further reduction in the peak of ground bounce noise during the sleep to active mode transition. The simulation results depicts that the proposed design leads to efficient 1bit full adder cell in terms of standby leakage power, active power, ground bounce noise and propagation delay. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.

The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a

IEEE Transactions on Electromagnetic Compatibility, 1992

This paper shows how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behaviors by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed and the influence of crosstalk on the behavior of basic functions such as logic gate, latch, RAM memory, and analog-to-digital converter are evaluated.