An analysis of high-frequency noise in RF active CMOS mixers

IEEE Transactions on Electron Devices, 2003

The RF noise in 0.18-m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for shortchannel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1 noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

IEEE Transactions on Microwave Theory and Techniques, 2010

This paper describes a design technique for a RF CMOS Low Noise Amplifier and Mixer. System level calculations are presented validating the feasibility of the proposed LNA/Mixer topology for its application. Tested and simulated in a 130-nm CMOS technology, the LNA achieves a minimum noise figure of 0.627dB, a noise figure of 0.833dB, and a forward-gain of 24.6dB at 600MHz from a 1.2-V supply.

IEEE Transactions on Electron Devices, 2001

An extraction method to obtain the induced gate noise ( 2 ), channel noise ( 2 ), and their cross correlation ( ) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.

Analog Integrated Circuits and Signal Processing, 2019

This paper presents an active down-conversion mixer for wireless local area network applications. The proposed downconversion mixer is designed for 2-3 GHz radio frequency (RF) band and an intermediate frequency of 100 MHz using RF-TSMC CMOS 0.18 lm technology. A new fully differential Darlington cell is introduced in the RF transconductance stage to effectively suppress third-order nonlinearity. In addition, the conversion gain and noise performance of the proposed mixer are improved by using an active load and current bleeding technique. The proposed mixer has been simulated by Cadence Spectre-RF. Post-layout simulation results show the third-order input intercept point can be improved up to 12.5 dBm by optimum biasing of the Darlington cell. The proposed mixer achieves the high conversion gain of 14.5 dB and the low double side-band noise figure of 4.55 dB at the input frequency of 2.4 GHz. The mixer operates at the supply voltage of 1.8 V with power consumption of 17.4 mW.

The present work consists of designing a Single Balanced Mixer(SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated. Keywords: SBM Mixer, Radio Frequency, 65 nm CMOS Technology, Non-Linearity, Power Consumption.

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013

This work presents an analysis of high frequency noise and linearity performance of a 90 nm CMOS process. Measurements are performed for a wide range of nominal gate lengths and bias points at high frequency. Modeling is based on the EKV3 compact model in Spectre RF circuit simulator from Cadence. The model shows correct scalability for noise and linearity accounting for short channel effects (SCEs), such as velocity saturation (VS) and channel length modulation (CLM). Results are presented versus a common measure of channel inversion level, named inversion coefficient. Optimum performance is shown to gradually shift from higher to lower levels of moderate inversion, when scaling from 240 nm to 100 nm. The same trend is observed from investigating the transconductance frequency product (TFP) of a common-source (CS) LNA for technology nodes ranging from 180 nm to 22 nm.

IEEE Transactions on Microwave Theory and Techniques, 2000

The noise figure of an RF CMOS mixer is strongly affected by flicker noise. The noise figure can be improved using pMOS switch circuits, which insert current at the on/off crossing instants of the local oscillator switch stage because the circuits reduce the flicker noise injection. When it is applied to a conventional Gilbert mixer, the injection efficiency and linearity are degraded by the nonlinear parasitic capacitances of the pMOS switch circuits and the leakage through the parasitic path. We propose the pMOS switch circuits with an inductor, which tunes out the parasitic components at 2 and closes out the leakage path. The mixer fabricated in 0.13-m CMOS at 2.4-GHz center frequency has provided improved characteristics for linearity and noise figure.

IEEE Transactions on Electron Devices, 2009

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS-also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (N F min ) as compared to classical MOSFET transistors (with the same gate length L g = 0.5 μm). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5-μm-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-μm-gate-length classical nMOS transistors.

IEEE Microwave and Wireless Components Letters, 2009

The impact of digital noise coupling through the substrate on RF MOSFETs was investigated in terms of the noise figure (NF) of the device up to 26.5 GHz. Previous works on the substrate digital noise coupling have treated the effect mostly in terms of the electrical isolation between ports, rather than actual devices, which does not provide direct information on the degradation of actual device performance parameters from such coupling. In this work, an actual NMOSFET was employed for test and the effect was described in terms of NF, a practical device performance parameter. The results show that NF is significantly degraded as the device enters the weak inversion state and/or ds becomes smaller, suggesting a trade-off between low power operation and immunity against the substrate noise coupling. Also, it is experimentally verified that devices with a dual guard ring showed much smaller NF than those with a single guard ring.