A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems

2017 42nd International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz), 2017

The design and performance analysis are presented for a passive uncooled radiometer pixel suitable for integration in 28nm CMOS technology. In the configuration a single wideband antenna, operating from 200 GHz to 600 GHz, is connected to a pn-junction diode. Including the antenna-detector impedance mismatch, the detector shows an average NEP of 2.71 pW/ √ Hz such that, together with the antenna, the radiometer promises fully passive and uncooled imaging capabilities with 2.6 K temperature sensitivity at a 10 Hz refresh rate. The design is planned for fabrication and measurement.

IEEE Journal of Solid-State Circuits, 2011

A W-band direct-detection-based receiver front-end for millimeter-wave passive imaging in a 0.18-m BiCMOS process is presented. The proposed system is comprised of a direct-detection front-end architecture employing a balanced LNA with an embedded Dicke switch, power detector, and baseband circuitry. The use of a balanced LNA with an embedded Dicke switch minimizes front-end noise figure, resulting in a great imaging resolution. The receiver chip achieves a measured responsivity of 20-43 MV/W with a front-end 3-dB bandwidth of 26 GHz, while consuming 200 mW. The calculated NETD of the SiGe receiver chip is 0.4 K with a 30 ms integration time. This work demonstrates the possibility of silicon-based system-on-chip solutions as lower cost alternatives to compound semiconductor multi-chip imaging modules.

IEEE Transactions on Microwave Theory and Techniques, 2000

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately +2 dBm and a phase noise of 90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1 noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 1 dB with respect to a 20.2-GHz input. The 0 3 0 3 mm 2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply. Index Terms-Frequency tripler, injection-locked, millimeterwave, quadrature voltage-controlled oscillator, regenerative peaking, wide locking range. I. INTRODUCTION E XCITING new opportunities are envisioned for silicon integrated circuits that are capable of mm-wave operation. Potential consumer applications include: gigabit per second short-range wireless communication in the 60-GHz (defined in the IEEE 802.15.3c standard) and 120-GHz bands, long-range collision avoidance radar for automobiles at 77 and 79 GHz, and sub-terahertz imaging (94 GHz and above) [1]-[3]. Production silicon VLSI technologies have demonstrated a peak transit frequency, , above 200 GHz for bipolar (NPN) devices [4], [5] and higher than 300 GHz for CMOS (NFET) transistors [6], [7], which has focused commercial interest towards millimeter-wave (mm-wave) frequency applications for silicon integrated circuits. Implementation of mm-wave transceivers in baseline CMOS technology is attractive because of its high potential for both low cost in volume production and RF/baseband co-integration. Single-sideband modulation or demodulation in a mm-wave transceiver requires a mm-wave local oscillator (LO) with quadrature (i.e., I and Q) outputs. A phase and amplitude tuning mechanism with about 5 and 0.5 dB [8] of correction range is required in order to tune out the unwanted sideband, as sideband rejection is often degraded by phase and amplitude

This paper presents an Ultra-Low-Power (ULP), high integration, and wide bandwidth low-IF radio frequency receiver for millimeter-wave (mm-wave) applications using 130 nm CMOS technology. The proposed radio receiver is composed of a low-noise driver stage implemented using a complementary current reuse common gate with an active shunt feedback configuration, and an in-phase/quadrature of phase (I/Q) demodulator. The driver stage is used to expand the input RF impedance matching with acceptable linearity and gain at an ultra-low DC power dissipation. Moreover, the transformer coupling between the trans-conductance and switching stages is used to separate the DC bias between those two stages, the transformer is a high coupling factor wideband width 5-ports transformer. The DC supplies of the proposed mm-wave radio frequency receiver are implemented using two energy-harvesting voltage doubler designs. The proposed mm-wave radio receiver dissipates 0.475 mW from a 1.1 V DC supply and it...

IEEE Microwave and Wireless Components Letters, 2016

A root-mean-square diode connected MOSFET detector for estimating the signal voltage of internal nodes of millimeter-wave circuits is demonstrated. These detectors fabricated in a foundry 65 nm CMOS process provide an affordable means for RF testing, built-in self-test as well as debugging of mm-wave circuits. This broadband detector operates from 80-110 GHz with detector gain of 8.5 V −1 at 60 nA bias. This in combination with high input impedance that results in less than 0.15 dB insertion loss relative to a thru structure, and a small area of 20 μm 2 makes the detector non-invasive.

This paper presents millimeter-wave CMOS building blocks for a high date rate wireless transceiver. The results include measured data for a 40-50 GHz broad-band low noise amplifier, a 40 GHz tuned power amplifier, and an 18 GHz voltage controlled oscillator. Also, simulation results for a 22 GHz multi-modulus prescaler is presented for implementing phase locked loop. The circuits were fabricated 0.13 ¿m CMOS process. The measured results showed good agreement with simulation data demonstrating good modeling accuracy of CMOS active and passive devices for millimeter-wave applications.

2009 IEEE MTT-S International Microwave Symposium Digest, 2009

Feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO and a 324-GHz quadruple pushed VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and 180-GHz Schottky diode and 780-GHz plasma wave detectors in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible.

IEEE Journal of Solid-State Circuits, 2000

A 2×2 array of 280-GHz Schottky-barrier diode detectors with an on-chip patch antenna is fabricated in a 130-nm logic CMOS process. The series resistance of diode is minimized using poly-gate separation (PGS), and exhibits a cut-off frequency of 2THz. Each detector unit can detect an incident carrier with 100-Hz~2-MHz amplitude modulation. At 1-MHz modulation frequency, the estimated voltage responsivity and noise equivalent power (NEP) of the detector unit are 250V/W and 33pW/Hz 1/2 , respectively. An integrated low-noise amplifier further boosts the responsivity to 80kV/W. At supply voltage of 1.2V, the entire chip consumes 1.6mW. The array occupies 1.5×0.8mm 2 . A set of millimeter-wave images with a signal-noise ratio of 48dB is formed using the detector. These suggest potential utility of Schottky diode detectors fabricated in CMOS for millimeter wave and sub-millimeter wave imaging.

International Journal of Microwave and Wireless Technologies, 2011

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this ...

IEEE Transactions on Microwave Theory and Techniques, 2000

We have developed a 27-and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18-m CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate -parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of 86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design.

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

This paper presents CMOS front-end ICs with 13.3 dBm output power for K-band FMCW radar, which is integrated in 0.13-μm CMOS technology. The transmitter consists of a voltage controlled oscillator, divider chain, power amplifier, and additional buffers. The receiver consists of a low-noise amplifier, IQ mixers, an IQ generator, and buffers. The leakage problem can be mitigated by adopting differential topology and ground shielding. As a result, the receiver achieves a conversion gain of 35.7 dB, a P1dB of-31.6 dBm, and a DSB noise figure of 5.5 dB. The transmitter achieves the tuning range of 23.8~24.5 GHz and the phase noise of-104 dBc/Hz @ 1MHz offset. The receiver and transmitter chips consume 121.5 mW and 373.5 mW from a 1.5 V power supply, respectively. Using these two chips, the K-band FMCW radar module is implemented and verified by measuring the distance of an object.

IEEE Journal of Solid-state Circuits, 2009

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10 11 BER.

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008

This paper presents a 1.2V, 100mW, 140GHz receiver with on-die antenna in a 65nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19dB in the 100-140GHz range with 102GHz LO, and occupies a die area of only 580µm × 700µm including pads. The LNA achieves 8dB gain at 140GHz, 10GHz bandwidth, at least -1.8dBm of saturated output power, and maintains 3dB gain at 125°C. The on-chip antenna, which meets all density fill requirements of 65nm CMOS, has -25dB gain, and occupies 180µm × 100µm of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

IEEE Transactions on Instrumentation and Measurement, 1999

A novel on-wafer resistive noise source, useful for noise characterization of microwave devices with the cold noise power measurement technique, is described. The noise source enhances measurement accuracy by providing a calibrated noise temperature directly at the device reference plane. A procedure for determining the excess noise ratio of the noise source is presented and validated up to 40 GHz. The noise source is employed in an on-wafer measurement system, allowing the noise parameters of two-port devices to be extracted. Following a description of the apparatus and measurement procedure, an example of a high-electron-mobility transistor noise parameter measurement at millimeter-wave frequencies is presented.