A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design

IEEE Transactions on Electron Devices, 2009

Achieving power-and area-efficient fully integrated transceivers is one of the major challenges faced when designing high-frequency electronic circuits suitable for biomedical applications or wireless sensor networks. The power losses associated with the parasitics of on-chip inductors, transistors, and interconnections have posed design challenges in the full integration of powerefficient CMOS radio-frequency integrated circuits (RF ICs). In addition, the parasitics of on-chip passive components that are integrated on lossy silicon substrates have made CMOS-based integrated circuits inferior to their compound-semiconductor counterparts. The parasitic effects of on-chip interconnections play a key role in RF circuit performance, particularly as the frequency of operation increases. Neglecting these effects leads to the significant degradation in circuit performance or even failure of operation in some cases. Furthermore, unlike transistors, miniaturization of interconnections does not improve their performance. This paper demonstrates the impact of metal layer resistivity and layout parasitics on an RF power amplifier (PA) and a low-noise amplifier (LNA). A nonlinear fully integrated 2.4-GHz class-E PA, with a class-F driver stage, and a 5-GHz LNA are discussed. The circuits were fabricated in a standard 0.18-μm CMOS technology. The layouts of the presented CMOS amplifiers were designed by carefully modeling the interconnection wires during the simulations and optimizing their widths for minimum parasitic effects and hence optimum measured circuit performance. Due to the careful layout design and interconnection optimization, the implemented amplifier circuits showed a good match between the measured and simulated performance characteristics.

International Journal of Computer Applications, 2016

This paper present a differential architecture of cmos transimpedance amplifier is offered to obtained the input capacitive load insensitive and the very minimum noise structure. The suggested TIA is dependent on the differential structure and composed of a regulated cascode block and a differential amplifier along with active feedback. To increase the bandwidth of the amplifier series inductive peaking and a capacitive degeneration step employed. Simulation results shows that the TIA achieves 100 GHz bandwidth, 80.4 dBΩ transimpedance gain, and 20 pA/

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new splitcapacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed. Summarizing, the methodology described in this paper simultaneously considers the interrelated issues of circuit speed, power dissipation, physical area, and system reliability, permitting the efficient design of tapered buffers.

A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it is connected with large capacitive load.The increasing width of each inverter in the chain of CMOS inverters is based on tapering factor.The scaling or tapering factor of each stage is dependant on technology used, driving load and the number of stages used.

The paper proposes a set of experiments with CMOS transistor array, which is a part of EDUCHIP test circuit. The goal of the experiments is to examine the dependence of the performance of CMOS amplifiers from bias current and W/L ratio of amplifying transistors. For that purpose different topologies of CMOS amplifying stages are presented and circuits for testing their basic small signal parameters and characteristics are discussed. Generalized tabular and graphical results from practical measurements are shown. They can be used in research and education on microelectronic circuits.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

Two prior-art transconductance amplifier-based rail-to-rail class-AB analog buffers are examined. Their analysis reveals that the output current drive capability for large input voltages is restricted. To mitigate this drawback, a relatively simple slew-rate enhancement scheme is proposed. The new scheme allows the buffer's speed to be increased by over 200% with only a very small increase in static power consumption (1.25%) and silicon area (3%). The proposed and the two conventional buffers were fabricated in a 0.35-μm CMOS technology for a power supply of 3 V. Measurements verify the superior slew-rate performance of the new buffer for rail-to-rail step responses.

2005

We present a new circuit technique for rail-to-rail constant-transconductance (gm) CMOS amplifier input stages, achieving constant transconductance and slew rate over the full input common-mode voltage range without degrading high-frequency performance. In addition, the technique does not rely on the quadratic characteristic of the input MOS transistors, and is robust to transconductance parameter mismatch between N and P input transistors. A CMOS amplifier input stage is designed in a standard 0.35-μm CMOS process. With a 3-V supply, the gm variation is kept within ±1% under nominal conditions and ±3% when there is ±40% mismatch of input transistor transconductance parameters. In addition, 114-MHz gain-bandwidth product is achieved with a 2 pF capacitive load. The proposed input stage can be applied in communications and VLSI cell libraries.

2009 European Conference on Circuit Theory and Design, 2009

A methodology for designing CMOS inverter-based output buffers considering speed, gain, jitter, and drivability requirements is presented. It adapts the band broadening technique of the classic Cherry-Hooper amplifier to CMOS inverters. A buffer designed this way offers higher speed than a commonly used simple chain of inverters with exponentially increasing gate widths. The buffer is implemented by making minor modifications to a 4-stage CMOS inverter chain. The proposed design is suitable for output buffers for high-speed CMOS logic circuits.

Low-Noise Amplifier (LNA), with a broadband circuit appears attractive because of the reduced cost realized by area reduction due to replacing of resistor with switch capacitor. The demand for a low-cost but high performance wireless front-end, many intensive researches on CMOS radio-frequency (RF) front-end circuit has been carried out. The goal is to minimize the cost and enhance the performance, low power consumption design. To design a Low Noise Amplifier one of the method which we have used is an inductor-less noise cancelling broadband using switch capacitor with composite transistor pair. The composite pair of NMOS/PMOS cross coupled transistor is used to amplify the input signal while reducing noise figure. It reduces the noise figure by partially cancelling noise which is generated by the input transistor pair. In this technique it does not rely on the matching between the devices which makes this architecture more beneficial to implement practically. Circuit implementation was done in cadence tools using gpdk90nm CMOS technology.

A transimpedance amplifier (TIA) has been designed in a 0.35 µm digital CMOS technology for Gigabit Ethernet. It is based on the structure proposed by Mengxiong Li [1]. This paper presents an amplifier which exploits the regulated cascode (RGC) configuration as the input stage with an integrated optical receiver which consists of an integrated photodetector, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. A series inductive peaking is used for enhancing the bandwidth. The proposed TIA has transimpedance gain of 51.56 dBΩ, and 3-dB bandwidth of 6.57 GHz with two inductor between the RGC and source follower for 0.1 pF photodiode capacitance. The proposed TIA has an input courant noise level of about 21.57 pA/Hz and it consumes DC power of 16 mW from 3.3 V supply voltage.