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2018, IEEE Transactions on Circuits and Systems I-regular Papers
The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shuntseries feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dB and an input-referred currentnoise spectral density of 39.8 pA/ √ H z over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm 2 (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).
Analog Integrated Circuits and Signal Processing, 2014
This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two commonsource stages with a 1.5 kX feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 X differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of-18.3 dBm for a bit error rate = 10-9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photocurrent range from 12 to 500 lA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBX and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm 2 whereas the complete optical receiver occupies a chip area of 0.46 mm 2. The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.
Journal of Computational Electronics, 2015
In this paper, a transimpedance amplifier (TIA)optical receiver (Rx) using two intersecting active feedback system with regulated-cascode input stage has been designed and fabricated for optical interconnects. The optical TIA-Rx chip is designed with 130 nm CMOS technology and operates up to 10 Gb/s data rate. The TIA-Rx chip core occupies an area of 0.051 mm 2 with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20pA/ √ Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 GHz /mW.
A transimpedance amplifier (TIA) has been designed in a 0.35 µm digital CMOS technology for Gigabit Ethernet. It is based on the structure proposed by Mengxiong Li [1]. This paper presents an amplifier which exploits the regulated cascode (RGC) configuration as the input stage with an integrated optical receiver which consists of an integrated photodetector, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. A series inductive peaking is used for enhancing the bandwidth. The proposed TIA has transimpedance gain of 51.56 dBΩ, and 3-dB bandwidth of 6.57 GHz with two inductor between the RGC and source follower for 0.1 pF photodiode capacitance. The proposed TIA has an input courant noise level of about 21.57 pA/Hz and it consumes DC power of 16 mW from 3.3 V supply voltage.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
A novel large-signal transimpedance amplifier frontend, intended for monolithic integration with a Si p-i-n diode and employing HBT-CMOS technology for use in short-range optoelectronic interconnects is proposed. Simulated bandwidth and gain are 4 Gbits/s and 43 dB, respectively, while driving a 100-fF load to TTL voltage levels.
Journal of Lightwave Technology, 2016
We have developed a 5 × 5 mm 2 compact siliconphotonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonicselectronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85°C. The minimum sensitivities and power consumptions of the receivers were −11.0 dBm and 2.3 mW/Gb/s at 25°C and −10.2 dBm and 2.5 mW/Gb/s at 85°C, respectively. These results show that our receiver can be applied for practical use at high temperatures.
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003
A 3.6 K-Ohm InP HBT transimpedance amplifier (TIA) has been demonstrated with a bandwidth of 60 GHz. Gain flatness of +/-2 dB and dc power of 271 mW has also been obtained. This TIA benchmarks the best gainbandwidth product (GBP) of 1.9 THz, the highest transimpedance-bandwidth product (TZ-BWP) of 216 Ohm-THz, and the highest TZ-BWP per dc power efficiency of +797 Ohm-GHz/mW obtained for a 40 Gb/s transimpedance amplifier. These results will be discussed in context with prior state-of-the-art 40 Gb/s TIAs implemented with various technologies and circuit topologies. 40 Gb/s photo-receiver requirements, TIA technology and topology trades, and future directions will be reviewed.
IEEE Microwave and Guided Wave Letters, 1998
Monolithically integrated SiGe/Si heterojunction bipolar transistor (HBT) transimpedance amplifiers, with single-and dual-feedback configurations, have been designed, fabricated, and characterized. The single-feedback amplifier showed transimpedance gain and bandwidth of 45.2 dB and 3.2 GHz, respectively. The dual-feedback version exhibits improved gain and bandwidth of 47.4 dB and 3.3 GHz, respectively. Their performance characteristics are excellent in terms of their application in communication systems.
This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiberoptic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.
International Journal on Smart Sensing and Intelligent Systems, 2011
This paper presents an integrated optical receiver which consists of an integrated photodetector, and a transimpedance circuit. A series inductive peaking is used for enhancing the bandwidth. The proposed structure operates at a data rate of 10 Gb/s with a BER of Iff20 and was implemented in a 0.35 μm CMOS process. The integrated photodiode has a capacitance of 0.01 pF which permits to the structure to achieve a wide bandwidth (5.75 GHz) with only one inductor before the last stage; hence a smaller silicon area is maintained. The proposed TIA has a gain of36.56 dBΩ (67.57 KΩ), and an input courant noise level of about 25.8 pA/Hz0.5. It consumes a DC power of 87.4 mW from 3.3 V supply voltage.
Microwave and Optical Technology Letters, 1993
and Cat each frequency instead of over a band of frequencies. The results show that both the channel noise term P and the correlation noise term C are constant with frequency across the entire frequency band. The gate-induced noise term R , does, however, drift slightly at the lower frequencies. At these lower frequencies the gate-induced noise contribution to the extrinsic noise parameters is small compared with that of the other two noise terms and as the parameter R stabilizes at higher frequencies when the gate-induced contribution is larger, this is thought to be the cause of the error seen. Also, at lower frequencies accurate measured values of extrinsic noise parameters, particularly R,, are difficult to obtain due to the high value of device input reflection coefficient. These points indicate that optimization over a band of frequencies in the higher range is preferable to a band in the lower range if accurate values of R are to be obtained.
Journal of the Optical Society of Korea, 2013
A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 μm CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 mm 2 with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/√Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 GHzΩ /mW.
Journal of Lightwave Technology, 2014
Highly integrated electronic driver and receiver ICs with low power consumption are essential for the development of cost-effective multi-channel fiber-optic transceivers with small form factor. This paper presents the latest results of a twochannel 28 Gbit/s driver array for optical duobinary modulation and a four-channel 25 Gbit/s TIA array suited for both NRZ and optical duobinary detection. This research demonstrated that 28 Gbit/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Ω, without degrading the signal quality. To the best of our knowledge this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 × 25 Gbit/s TIA shows a good sensitivity of −10.3 dBm average optical input power at 25 Gbit/s for PRBS 2 31 − 1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process.
2018 European Conference on Optical Communication (ECOC), 2018
We present a silicon optical receiver consisting of a low-noise fully-differential transimpedance amplifier with on-chip biasing for a SiPh Ge PD. Error-free (BER < 10-12) 56Gb/s NRZ operation is demonstrated with a record OMA sensitivity of-10.2dBm at 170mW.
2018 IEEE 10th International Conference on Humanoid, Nanotechnology, Information Technology,Communication and Control, Environment and Management (HNICEM), 2018
A transimpedance amplifier for optical communication system is presented in this study. The design includes a regulated cascode and an interleaving active feedback to improve the bandwidth of the transimpedance amplifier. Multiple gain stages are also employed to greatly improve the output voltage. This is implemented in 32 nm CMOS technology using Custom Designer from Synopsys. The circuit is designed to compete with existing transimpedance amplifiers implemented in other technologies in the field of optical communications. The transimpedance amplifier design in this study has a gain of 54 dB and a bandwidth of 9.39 GHz. The layout measures 0.0011mm2 in area and the total power dissipated is 2.94 mW
48th Midwest Symposium on Circuits and Systems, 2005., 2005
This paper presents a new high performance wideband CMOS transimpedance amplifier (TIA) for 2.5 Gbps optical transceiver. Our proposed TIA self-regulating adjusts the controllable inductive peeking load and feedback resistances whenever overload condition occurs. The proposed TIA design exhibits bandwidth enhancement, lower input referred noise, and higher amplifier stability. This TIA has 69dBΩ gain at 3dB bandwidth, 7.2 / pA Hz input referred noise and good performance of eye diagram. The TIA operates at the 3.3V supply voltage, and dissipates about 34mA for whole circuit. The simulation is accomplished with 1pF capacitance and 0.85A/W responsibility photodiode model. I.
Microwave and Optical Technology Letters, 2001
2017
This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.
IEEE Journal of Solid-state Circuits, 2003
InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dBtransimpedance and 49-GHz bandwidth.
Microwave and Optical …, 1998
A technology-independent design solution, based on induc-ti¨e peaking and feedback techniques, is described and applied to the design of GaAs integrated amplifiers for optical recei¨ers. Transimpedance and gain peaking amplifiers are cascaded to increase the gain and to reduce the effect of the photodetector diode parasitic capacitance on the transimpedance bandwidth. A monolithic test¨ehicle of the methodology has been realized: measured performances include a transimpedance gain of 65 dBQ and a bandwidth of 3.4 GHz from quasi-dc for the unloaded amplifier. The estimated bandwidth, using a low-cost 1 pF input photodiode, is 1.9 GHz, fulfilling the system needs for 2.5 Gbitr s optical links.
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