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2014, IEEE Journal of Solid-State Circuits
A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of -77.8 dBc/Hz (-82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32-303.36 GHz (7.9%).
IEEE Transactions on Microwave Theory and Techniques, 2012
Two monolithically integrated W-band frequency synthesizers are presented. Implemented in a 0.18 m SiGe BiCMOS with of 200/180 GHz, both circuits incorporate the same 30.3-33.8 GHz PLL core. One synthesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1 GHz and the other employs a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5 GHz from 90.9-101.4 GHz, respectively. The measured RMS phase noise for ILFT-and HBFT-based synthesizers are 5.4 and 5.5 (100 kHz to 100 MHz integration), while phase noise at 1 MHz offset is and dBc/Hz, respectively, at 96 GHz from a reference frequency of 125 MHz. The measured reference spurs are dBc for both prototypes. The combined power consumption from 1.8-and 2.5-V is 140 mW for both chips. The frequency synthesizer is suitable for integration in millimeter-wave (mm-wave) phased array and multi-pixel systems such as W-band radar/imaging and 120 GHz wireless communication.
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012
A highly efficient push-push voltage controlled oscillator (VCO) with a new varactor-less-based frequencytuning topology for terahertz (THz) frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base degenerated transistor. Fabricated in a 130nm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and output power of − − − −7.2 dBm at 201.5GHz. The VCO consumes 30mW of DC power, resulting in a record-breaking power efficiency of 0.6%. To demonstrate the functionality of the tuning technique, three other VCO prototypes at different oscillation frequencies, including one operating at 222.7~229 GHz range, have been implemented. Index Terms-Voltage controlled oscillator (VCO), Colpitts oscillator, Clapp oscillator, varactor-less tuning, inductive tuning, sub-millimeter wave, terahertz (THz).
IEEE Transactions on Microwave Theory and Techniques, 2013
IEEE Transactions on Microwave Theory and Techniques, 2000
A highly efficient push-push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13-m SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of 7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit of 165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7-229-GHz range, are implemented and measured.
Progress In Electromagnetics Research C, 2014
In this paper, a 42 GHz frequency synthesizer fabricated with 0.13 µm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic (CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base structure is used in the frequency doubler design to widen the bandwidth and improve the fundamental rejection. The doubler shows a 41% fractional 3 dB bandwidths with a fundamental rejection better than 25.7 dB. The synthesizer has a maximum output power of 0 dBm with a DC power consumption of 60 mW. The worst phase noise at 100 kHz, 1 MHz and 10 MHz offset frequencies from the carrier is −71 dBc/Hz, −83 dBc/Hz and −102.4 dBc/Hz, respectively.
2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008
A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 1 dB with respect to a 20.2-GHz input. The 0 3 0 3 mm 2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply. Index Terms-Frequency tripler, injection-locked, millimeterwave, quadrature voltage-controlled oscillator, regenerative peaking, wide locking range. I. INTRODUCTION E XCITING new opportunities are envisioned for silicon integrated circuits that are capable of mm-wave operation. Potential consumer applications include: gigabit per second short-range wireless communication in the 60-GHz (defined in the IEEE 802.15.3c standard) and 120-GHz bands, long-range collision avoidance radar for automobiles at 77 and 79 GHz, and sub-terahertz imaging (94 GHz and above) [1]-[3]. Production silicon VLSI technologies have demonstrated a peak transit frequency, , above 200 GHz for bipolar (NPN) devices [4], [5] and higher than 300 GHz for CMOS (NFET) transistors [6], [7], which has focused commercial interest towards millimeter-wave (mm-wave) frequency applications for silicon integrated circuits. Implementation of mm-wave transceivers in baseline CMOS technology is attractive because of its high potential for both low cost in volume production and RF/baseband co-integration. Single-sideband modulation or demodulation in a mm-wave transceiver requires a mm-wave local oscillator (LO) with quadrature (i.e., I and Q) outputs. A phase and amplitude tuning mechanism with about 5 and 0.5 dB [8] of correction range is required in order to tune out the unwanted sideband, as sideband rejection is often degraded by phase and amplitude
IEEE Journal of Solid-State Circuits, 2004
The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as 70 dBc and the phase noise is lower than 116 dBc/Hz at 1 MHz over the whole tuning range.
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003
In this paper, we present a 10/30 CHz MMIC tripler using a 0.35 pm, 60 GHafMAx BiCMOS SiCe technology. It exhibits a conversion gain in the-5 dB range, a fundamental rejection between-12 and-24 dB over an input dynamic range of 1-5; 31 dBm. A low additive phase noise of-143 dBcJHz at a frequency offset of 100 kHz is anticipated. The DC power consumption is 440 mW. The chip surface i s 800x650 pm' (0.4 mm2 only without the probe pads area). In order to drive this tripler, the design of a MMIC SiCe Xband VCO and its measured performance (0.8 GHz tuning range,-5 dBm output power and-87 dBc/Hz phase noise @ 100 kHz off carrier) is also reported. I.
IEEE Journal of Solid-State Circuits, 2000
A balanced Colpitts voltage-controlled oscillator (VCO) is designed and fabricated in a commercially available 0.25m SiGe BiCMOS process. It has the characteristics of the push-push VCO, i.e., the VCO has simultaneously a differential output at a fundamental frequency of 21.5 GHz and a single-ended output at the second harmonic frequency of 43 GHz. A differential tuning technique is applied to reduce the phase noise. The measured phase noise at 1-MHz offset is 113 dBc/Hz at 21.5 GHz and 107 dBc/Hz at 43 GHz. The corresponding output power is about 6 and 17 dBm, respectively, with a 5% tuning range and a 130-mW dc power consumption.
2007 IEEE International Workshop on Radio-Frequency Integration Technology, 2007
Two 130nm CMOS VCOs with ferroelectric varactors are presented. The cross-coupled VCO-cores are flip-chip mounted on silicon carriers with integrated inductors and tunable ferroelectric varactors. The output frequency of the first VCO is tunable from 23.4 GHz to 26.1 GHz, corresponding to a tuning range of 11 %. The phase noise of this VCO, tuned to its center frequency, measures-117 dBC/Hz at 1 MHz offset and the power consumption is 18 mW. The second VCO is tunable from 25.8 GHz to 30.5 GHz, corresponding to a tuning range of 17 %. The phase noise at center frequency for this design measures-109 dBc/Hz and the power consumption is 5.3 mW Index Terms-VCO, ferroelectric, BSTO, varactor.
2007 IEEE Compound Semiconductor Integrated Circuits Symposium, 2007
We present a fully integrated phase-locked loop tunable from 17.5 GHz to 19.2 GHz fabricated in a 0.25 µm SiGe BiCMOS technology. The measured phase noise is below -110 dBc/Hz at 1 MHz offset over the whole tuning range. Based on an integer-N architecture, the synthesizer consumes 248 mW and occupies a chip area of 2.1 mm 2 including pads. Quadrature outputs at quarter of the oscillator frequency are produced, which are required in a sliding-IF 24 GHz transceiver. Possible applications include wireless LAN as well as satellite communication. The measured phase noise is the lowest among previously published Si-based integrated synthesizers above 12 GHz. Index Terms -Phase-locked loop, wireless LAN, SiGe, BiCMOS, phase noise, 24 GHz.
… Integrated Circuits in …, 2009
2008 IEEE Compound Semiconductor Integrated Circuits Symposium, 2008
A SiGe millimeter-wave VCO with a center frequency of 80 GHz and an extremely wide (continuous) tuning range of 23 GHz (29%) is presented. The phase noise is ≈ -95.5 dBc/Hz (at 1 MHz offset frequency) and the total output power ≈ 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW). A lowpower frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitations of the tuning range in MMW-VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4-11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOM T and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only 0.1 ×0.395 µm 2 .
IEICE Transactions on Electronics, 2015
In this paper, a 97-mW 8-phase CMOS voltage-controlled oscillator (VCO) and dividers covering the entire VCO oscillation range for a 134-GHz phase-locked loop (PLL) synthesizer are presented. The dividers have two injection-locked frequency dividers (ILFDs), one with and one without an inductor, and a pulse-swallowing counter with a differential dual-modulus prescaler. The VCO has a fundamental oscillation frequency range of 131.8 GHz to 134.3 GHz, achieved by controlling the back-gate voltage, which is also used to tune the locking range of divide-by-2 and divide-by-3 dividers. The ratio between the measured VCO oscillation frequencies and output frequencies of dividers is in good agreement with the target ratio. This indicates that the dividers covered the entire VCO oscillation range. We fabricated the VCO and dividers with a chip core area of 180 μm × 100 μm implemented in a 65-nm CMOS process. The total power consumption was 97 mW at a 1.2-V supply voltage.
Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009
This paper presents a low-power/low-voltage frequency synthesizer for the frequency of 2.4 GHz, which were designed and fabricated in a standard 0.18 Pm CMOS process. This synthesizer is based on a Phase-locked Loop (PLL) with a integer divider in the feedback loop and for a voltage supply of only 1.8 V, it presents a total power consumption of 3.4 mW. The power consumptions for the Voltage-controlled oscillator, phase-frequency difference/charge-pump and for the divider are 2 mW, 1 mW, 420 PW, respectively. The PLL is very fast, e.g., it takes only 1.6 Ps to lock, which makes it a perfect companion for devices where frequency hops must be done very quickly.
IEEE Journal of Solid-State Circuits, 2000
This paper proposes a sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for millimeter-wave Time-division Duplexing (TDD) transceivers. The proposed synthesizer is capable of supporting all 60 GHz channels (58.1-65 GHz) including channel-bonding defined by 60 GHz wireless standards for short-range high-speed wireless communications. In order to guarantee a robust performance over process-voltage-temperature (PVT) variations of the conventional frequency synthesizer, a frequency calibration scheme is proposed to automatically correct a frequency drift of quadrature injection locked oscillators. Implemented by a 65 nm CMOS process, the frequency synthesizer achieves a typical phase noise of 117 dBc/Hz @ 10 MHz offset from a carrier frequency of 61.56 GHz while consuming 72 mW from a 1.2 V supply. The calibration system consumes 65 mW additionally.
2008
Abstract The design of a millimeter-wave dual-band phase-locked frequency synthesizer in a 0.18 mum SiGe BiCMOS technology is presented. All circuits except the voltage controlled oscillators (VCOs) are shared between the two bands. A W-band divide-by-3 frequency divider is used inside the loop after the VCOs to simplify division-ratio reconfiguration. The 0.9 mm 2 synthesizer chip exhibits a locking range of 23.8-26.95/75.67-78. 5 GHz with a low power consumption of 50-75 mW from a 2.5 V supply.
Radio Frequency …, 2003
IEEE Journal of Solid-State Circuits, 2000
A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( 30%) is presented. The phase noise at 1 MHz offset is 97 dBc/Hz at the center frequency (and less than 94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.
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