A novel ultra high-speed flip-flop-based frequency divider

IJIRST, 2014

A low power 1MHz Full programmable frequency divider in 45-nm CMOS process is presented in this paper. The divide ratio can be varied from 2400 to 2431 in a step size of 1.The divider consists of a divide-by-2 circuit, divide-by-2/3 prescaler, divide-by-32/33 prescaler, a programmable pulse-swallow counter. The post simulation results demonstrate that the divider can operate with the input frequency ranging from 2.46GHz-2.541GHz. Measured results show that programmable divider consuming only 613.39 µW at 1V power supply. The programmable frequency divider is design and simulated on Tanner EDA Tool using 45nm CMOS process technology with supply voltage 1 V.

2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology, 2017

This paper presents a topology which gives optimum performance in terms of operating frequency, speed of operation, power dissipation, Power Delay Product (PDP) and transistor count .The operation of the latch shown is controlled by the p-MOS and the n-MOS switches. Cascading two stages of the proposed latch incorporates a 'divide by 2' circuit whose simulation result is shown in Fig.2. The proposed circuit uses 12 MOSFETs which is lesser as compared to other topologies and consumes a power of 216 W operating at a frequency of 0.5 GHz and a supply of 1.8 V. The proposed circuit has a very low average delay of 300 ps at 1.8 V supply, which makes it a better contender in high speed Frequency Synthesizers .The proposed circuit has a PDP of 6.48 x10-14 J .The proposed circuit has been simulated in Cadence Virtuoso using 180 nm CMOS Technology and a supply of 1.8 V

IAEME PUBLICATION, 2014

Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL, which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The designed Frequency divider has been used in the divider counter of the phase locked loop. A divide counter is required in the feedback loop to scales down the frequency of the VCO output signal. The conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of Cadence have used to design and simulate schematic. This work has been used in the design of 2.4 GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption.

2006 IEEE North-East Workshop on Circuits and Systems, 2006

This paper presents the design of a high-speed wide-band frequency divider. The divider core is formed with a low voltage swing current mode logic (CML) structure, which enables high frequency operation at very low power dissipation. The divider exhibits very wide locking range from 4GHz-41GHz, and it has an input sensitivity of-31dBm at 30GHz. The divider core draws only 750µA from a 1.2V supply. Post layout simulation results in 90-nm CMOS technology are provided.

Proceedings of SPIE, the International Society for Optical Engineering, 2007

Résumé/Abstract High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers allow the output frequency from a voltage controlled oscillator to be compared with a much lower external reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper we demonstrate the design of a high frequency, low power divider in 0.18 μm SiGe ...

2007 IEEE Compound Semiconductor Integrated Circuits Symposium, 2007

A 2:1 static frequency divider using a bandpass load was fabricated in a digital 90nm SOI CMOS technology. The divider exhibits a maximum operating frequency of 81GHz at 1.2V, and a core power of 15.6mW. The divider can operate down to 0.5V at a maximum operating frequency of 75.6GHz with a core power of 2.75mW.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25-m SOS-CMOS technology, occupies 35 25 m 2 and exhibit a operating frequency of 5.6 GHz while consuming 79 W at a supply voltage of 0.8 V. Process and temperature tolerant operation can be achieved by utilizing a novel compensation circuitry to calibrate the speed of the ring oscillatorbased divider. The simple compensation circuitry contains lowspeed digital logic and dissipates minimal additional power since it is powered on only during the one-time factory calibration sequence.

2003

A 2:1 static frequency divider was fabricated in a 0.12-μm SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

IEEE Microwave and Wireless Components Letters, 2000

This paper presents a 0.13 µm CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of its phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19 GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15 GHz, 31% locking range. The divider dissipates 3 mA from 1.2 V power supply.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.

IEEE Microwave and Wireless Components Letters, 2005

This paper presents a 0.13 µm CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of its phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19 GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15 GHz, 31% locking range. The divider dissipates 3 mA from 1.2 V power supply.

Smart Structures, Devices, and Systems III, 2006

High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers allow the output frequency from a voltage controlled oscillator to be compared with a much lower external reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency synthesizer. The simulation results are in agreement with measured performance of the regenerative divider. At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to 36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.

This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of output voltages derived from differential equations of the large-signal model of the circuit. Tradeoffs and design techniques for very high frequency dividers have been discussed on the basis of the derived expression. An inductor-less 45 GHz divider and a shunt-peaked 60 GHz divider have been designed in 0.13 µm process following the suggested design techniques. Detailed simulation results have been presented.

Digest of Papers. 2005 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2005., 2005

This paper reports a 71 GHz static and a 103 GHz regenerative dynamic frequency divider fabricated in 0.25 µm SiGe:C HBT technology with f T /f max 200 GHz. The static divider including the buffer works with a 3.5 V single supply voltage and consumes 140 mW with 42 mW for the master-slave flip-flop (FF). The high speed/power ratio makes it attractive for high-frequency wireless communication systems. The dynamic frequency divider operates from 24 GHz to 103 GHz with 5.2 V voltage supply and consumes 195 mW including the buffer with 41 mW for the divider core, and it can be applied at higher frequencies in low power millimeter wave systems.

IET Circuits, Devices & Systems, 2007

A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-mm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.