A novel linearization technique for linear/pseudo-linear RF CMOS power amplifiers

NORCHIP 2012, 2012

Radio frequency power amplifiers (PAs) play a keyrole in transceivers for mobile communications and their linearity is a crucial aspect. In order to meet the linearity requirements dictated by the standard at a reasonable efficiency, the usage of a linearization technique is required. In this paper we propose a linearization by means of a new type of digital predistorter, defined directly in the I-Q domain. The architecture of the proposed predistorter can be understood as an enhancement of the memory polynomial model (MPM) by means of additional I-Q terms. The usage of the proposed predistorter allows a more robust linearization of the whole RF transmitter because the enhancement of the model with additional I-Q terms can guarantee a more versatile compensation which is beneficial when the distortion comes from the joint contribution of the PA and the quadrature modulator. The proof of concept is achieved by measurements on a commercial PA in GaN technology and the performance of the proposed predistorter is illustrated.

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD3 improved by 14 dB, OIP3 improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved.

IEEE Microwave Magazine, 2000

Concurrent Linearization ith the explosive growth of the smartphone and tablet markets, wide bandwidth voice and data communication have become ubiquitous. Users expect to use their wireless portable phone/computing devices at any place and at any time. Furthermore, with the today's economy of scale, yesterday's high-performance devices are today's entry-model devices. To make possible this global wide-bandwidth wireless communication and networking while handling the increasing number of users, new wireless communication standards based on high bandwidth efficiency protocols such as orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA) have been developed to meet the user capacity requirements. These new communication standards have, however, placed very challenging demands on the RF front-end specifications in terms of bandwidth and power efficiency for both hand-held devices and base stations. Indeed, a characteristic of OFMD and CDMA signals is that they feature very high peak to average power ratios (PAPR), typically on the order of 10 dB even after crest factor reduction techniques or softclipping. Thus, for example, an 80 W average power base-station power amplifier (PA) should be able to also amplify linearly outburst, with 800 W instantaneous peak power. Special RF amplifiers are then needed to amplify such signals with large PAPR while providing high average power efficiency. However, power efficiency in PA operation comes in practice at the cost of increased nonlinearities. As is well known, nonlinearities lead not only to inband signal distortion but also to outband spectral regrowth, which are strictly regulated. A provider cannot pollute the band of a competitor. Thus, linearization techniques are used to linearize the amplifiers and reduce the inband signal distortion and outband spectral regrowth to acceptable levels.

2002

± %DUFHORQD 6SDLQ (PDLO EHUWUDQ#WVFXSFHV $EVWUDFW. A compensation technique for the amplitude and phase imbalances of a feedforward lineariser using the LMS algorithm, implemented entirely in the analog domain, is presented. The lineariser is suited to RF power amplifiers, and maybe entirely developed with analog IC technologies. From simulated two-tone tests, the circuit leads to an intermodulation (IMD) reduction superior to 35 dB for a 64-QAM signal, being cheaper and competitive in performance with usual DSP-based adaptation circuits. Different implementations are evaluated, and the application of the circuit to RF power amplifiers in the DVB-T and in the LMDS frequency bands is considered. .H\ZRUGV )HHGIRUZDUG OLQHDULVHU SRZHU DPSOLILHUV /06 DOJRULWKP DQDORJ VLJQDO SURFHVVLQJ DQDORJ LQWHJUDWHG FLUFXLWV 2 $QDORJ ,&$FKLHYDEOH /LQHDULVHU IRU 3RZHU $PSOLILHUV EDVHG RQ $GDSWLYH )HHGIRUZDUG $EVWUDFW. A compensation technique for the amplitude and phase imbalances of a feedforward lineariser using the LMS algorithm, implemented entirely in the analog domain, is presented. The lineariser is suited to RF power amplifiers, and maybe entirely developed with analog IC technologies. From simulated two-tone tests, the circuit leads to an intermodulation (IMD) reduction superior to 35 dB for a 64-QAM signal, being cheaper and competitive in performance with usual DSP-based adaptation circuits. Different implementations are evaluated, and the application of the circuit to RF power amplifiers in the DVB-T and in the LMDS frequency bands is considered. ,QWURGXFWLRQ New telecommunications products, such as the terrestrial segment of the digital television (DVB-T) or the new LMDS loops need efficient RF power amplifiers with high linearity. Energy efficient power amplifiers are pushed near to the limits of performance, operating in the gain fall-off region (compression point), where the nonlinear behavior is significant. Simple alternatives, such as the use of multiple bipolar transistors operating in parallel, each one far from its compression point, show high linearity at the price of significantly increased power dissipation and amplifier costs. Among modern multi-carrier communication systems, linearisation techniques offer an alternative to the use of multiple power transistors, and the feedforward linearisation structure is currently the most effective [1].

Journal of Circuits, Systems and Computers, 2011

In this paper, a new linearization algorithm of power amplifier (PA), based on Kalman filtering theory is proposed for obtaining fast convergence of the adaptive digital predistortion. The proposed method uses the real-time digital processing of baseband signals to compensate the nonlinearities and memory effects in radio-frequency power amplifier. To reduce the complexity of computing in classical Kalman filtering, a sliding time-window has been inserted which combines offline measurement and online parameter estimation with high sampling time to track the changes in the PA characteristics. The performance of the proposed linearization scheme is evaluated through simulation and experiments. Using digital signal processing, experimental results with commercial power amplifier are presented for multicarrier signals to demonstrate the effectiveness of this new approach.

2009

In the present paper, the nonlinear Internal Model Control (IMC) method is introduced and applied to linearize high frequency Power Amplifiers (PAs). The IMC is based on the description of a process model and of a controller. It is shown that baseband frequency descriptions are suitable for the model and the controller. Their description parameters are derived from input and output modulation signals processed in Cartesian form. Simulation results are given to illustrate the design procedure and to demonstrate the performances of the IMC linearizer.

Analog Integrated Circuits and Signal Processing, 2002

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Ω load. A design method to find the large signal parameters of the output transistor is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3π/8-8PSK) modulated signal.

ICIECA 2013, 2013

A new circuit concept to improve the maximum linear output power of a Universal Mobile Telecommunication System (UMTS) power amplifier (PA) is introduced in this paper. The proposed circuit consists of an analog pre-distorter (APD) integrated at the input of a class B amplifier. The proposed APD extends the maximum linear output power of the PA to 28dBm with corresponding power added efficiency (PAE) of 52.3%. Simulation result shows that at 1.95GHz, PA has a worst case adjacent channel leakage ratio (ACLR) of -36dBc at output power of 28dBm. With a respective input and output return losses of -27.6dB and -13.2dB, the PA’s power gain is simulated to be 33.3dB while exhibiting an unconditional stability characteristic from DC to 3GHz. The monolithic microwave integrated circuit (MMIC) power amplifier (PA) is designed in 2μm InGaP/GaAs process. The proposed APD technique serves to be a good solution to improve the maximum linear output power of the UMTS PA without sacrificing other critical performance metrics.

2003

The linearity of CMOS is analyzed. 'Ikansconductance and output conductance are two dominant nonlinear sources of CMOS. Capacitances and substrate leakage network do not generate any significant distortions. But they reduce the output impedance for the best linearity and the power gain at a high frequency and the output conductance nonlinearity is significantly at a high frequency. Up to a few GHz, the output conductance is the dominant nonlinear source, and at a higher frequency, the transconductance is the dominant nonlinearity source. OIP3 is reduced by the effects of those components. OIP3s are calculated for various gate length processes. CMOS linearity is dependent only on current density and drain bias voltage but is not dependent on gate length.

High Frequency Electronics, 2006

Power amplifiers (PAs) are vital components in many communication systems. To be transmit-ted wirelessly, a signal must be amplified with high fidelity so as to account for attenuation through the channel or propagation medium. The linearity of a PA response constitutes ...

IEEE Journal of Solid-State Circuits, 2006

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by 3 and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5 dBm of 1dB with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under 45 dBc of IMD3 and 57 dBc of IMD5 when the output power is backed off by more than 5 dB from 1dB. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification. Index Terms-Differential power amplifier, error vector magnitude (EVM), even in-phase harmonics, harmonic termination, odd anti-phase harmonics, Volterra series. I. INTRODUCTION A S THE PROLIFERATING wireless personal communication systems require multi-function capability with miniaturization, the CMOS process, which has the merit of high-level integration, becomes the technology of choice for the solution. With the continued scaling of CMOS technology, the multifunction RF transceivers including the baseband and IF blocks, could be integrated in a single chip. Many efforts have also been made to implement RF CMOS power amplifier (PA)

JSTS:Journal of Semiconductor Technology and Science, 2009

Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiers in the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.

—The design of a 2.4 GHz Doherty radio frequency (RF) power amplifier (PA), suitable for fabrication in a 180 nm complementary metal-oxide semiconductor (CMOS) process, is presented. The main amplifier is biased in class AB. The load modulation effect is achieved by an auxiliary amplifier biased in class C followed by a dephasing network. Digital baseband predistortion (DPD) based on a multi-layer perceptron artificial neural network model is applied to linearize the designed PA. Circuit-level simulations are reported to validate the designed PA. In a first analysis, a one-tone RF stimulus signal is applied. Using a 3.3 V supply, the PA achieves 25.9 dBm of maximum output power, as well as a peak power added efficiency (PAE) equal to 34.1%. In compression point (OCP1) the PAE is about 29.3%. At 6-dB back-off the PA has a PAE of 18.5%. In a second analysis, a modulated RF carrier is applied and the linearities of PAs with and without DPD are compared under the same average output power. In case of an OFDMA signal, the inclusion of the linearizer reduces the adjacent channel power ratio (ACPR) by about 23 dB and the error vector magnitude (EVM) is decreased from 15.9% to 0.6%. In case of a WCDMA signal, improvements around 25 dB in ACPR results, as well as a decrease in EVM from 8.8% to 0.7%, are achieved by the inclusion of the linearization.

International Journal of RF and Microwave Computer-Aided Engineering, 2005

Developments in new and classical RF solid-state power amplifier (SSPA) linearisation techniques, within the context of the EU TARGET ("Top Amplifier Research Groups in a European Team") Network of Excellence's (NoE's) coordination of research in this field, are reviewed. The issues addressed include feedforward, digital, and analog predistortion; feedback (at both circuit and system levels); and context-based bounds for linearisation benefits.

2008