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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)
In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided, and a new performance metric for the energy optimization under the delay constraint is proposed. The energy formulations are obtained by using approximated expressions for the driving-point impedance of lossy coupled transmission lines which itself is derived by solving Telegrapher's equations. A comprehensive analysis of energy is performed for a wide variety range of the gate aspect-ratios of the driving transistors. To accomplish this task, two stable circuits that are capable of modeling the transmission line for a broad range of frequencies are synthesized. Experimental results show that the energy calculated using these equivalent circuits are almost equal to the one calculated by solving the more complicated transmission line equations directly. Next, using a new performance metric the effect of geometrical variations of the interconnect and the driver on the energy optimization under the delay constraint is studied. The experimental results verifies the accuracy of our models.
2002
Abstract In this paper new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided. These formations are obtained using an approximated expression for the driving-point impedance of loss coupled transmission lines which itself is derived by solving Telegraphers equations. A comprehensive analysis of energy if performed for both step and flattened ramp inverter inputs.
Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS/X simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the shortcircuit to dynamic power is less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. Therefore, the total power consumption is expected to decrease as inductance effects becomes more significant as compared to an RC model of the interconnect.
2003
Abstract This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing.
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1999
dfm [151, j161. Furthermore performance requirements are accelerating the introduction of neu' materials such as low resistivity copper interconnect 1171. In the limitine case, high temperature superconductors may possibly become commerciall) available [IS]. More accurate RLC transmission line models are therefore becoming necessary in the analysis of VLSI-based interconnect.
This paper presents a novel approach for delay modeling of Inverter followed by Transmission Gate (Inv-TG) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitance while treating the Inv-TG structure as a single entity. Subsequently, we propose a methodology to incorporate the effect of Process-Voltage-Temperature (PVT) variations in the derived model. We compare our derived model against the SPICE simulation results using 32nm Predictive Technology Model. We observe that the error in the estimated delay using our model is within the acceptable range (< 10%).
Analog Design Issues in Digital VLSI Circuits and Systems, 1997
A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha power law and exhibits good accuracy. The model can be used to design and analyze those inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay, transition time, and short circuit power dissipation for a CMOS inverter driving resistive-capacitive interconnect lines.
A scattering parameter-based homogeneous distributed line model with arbitrary initial and boundary conditions is proposed and its implementation in a general purpose circuit simulator supporting user functions is described.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-m TSMC CMOS technology and applied to a 4500-m long Metal4 bus. Circuit simulation results for different bus widths are presented.
IEE Proceedings - Circuits, Devices and Systems, 1998
An accurate, analytical model is presented for the evaluation of the CMOS inverter delay in the submicron regime. Following an exhaustive analysis of the inverter operation, accurate expressions of the output response to an input ramp are derived, which result in the analytical calculation of the propagation delay. These expressions are valid for all the inverter operation regions and input waveform slopes, and take into account the influences of the shortcircuit current and the gate-drain coupling capacitance. The effective output transition time of the inverter is determined, in order to map the real output waveform to a ramp waveform for the model to be applicable to CMOS gate chains. The results are in very good agreement with SPICE simulations.
2013
Ever increasing fraction of the energy consumption of an Integrated circuit is due to the interconnect wires (and the associated driver and receiver circuits). Power dissipation from the interconnect wires amounts to up to 40% of the total on-chip power dissipation in some gate array design styles. When compared with other techniques a diode-connected driver circuit has the best attributes over other low-swing signaling techniques in terms of power, and delay. The proposed signaling schemes of symmetric lowswing driver-receiver pairs (MJ-SIB) and (MJDB) for driving signals on the global interconnect lines, which are implemented using split R-π model for an interconnect line, provides best results.
IJEER, 2014
In this paper, an analysis of different delay lines based on CMOS architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines.
2004
Abstract This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing.
IEEE Transactions on Microwave Theory and Techniques, 2001
This paper presents a new method for the extraction of the frequency-dependent, per-unit-length (p.u.l.) resistance, and inductance parameters of multiconductor interconnects. The proposed extraction methodology is based on a new formulation of the magneto-quasi-static problem that allows lossy ground planes of finite thickness to be modeled rigorously. The formulation is such that the p.u.l. impedance matrix for the multiconductor interconnect is extracted directly at a prescribed frequency. Once the matrix has been calculated over the bandwidth of interest, rational function representations of its elements are generated through a robust matrix curve-fitting process. Such a formulation enables subsequent transient analysis of interconnects through a variety of approaches. Direct incorporation of the rational function model into a general-purpose circuit simulator and a standalone multiconductor-transmission-line simulator is demonstrated.
IEEE Transactions on Microwave Theory and Techniques, 1999
A passive closed-form model for multiconductor lossy transmission line analysis is presented in this paper. The proposed model is suitable for inclusion in general-purpose circuit simulators and overcomes the mixed frequency/time simulation difficulties encountered during the transient analysis. In addition, the model can handle frequency-dependent line parameters. This method offers an efficient means to discretize transmission lines compared to the conventional lumped discretization, while preserving the passivity of the discrete model. Coefficients describing the discrete model are computed a priori and analytically, using closed-form Padé approximants of exponential matrices. Numerical examples are presented to demonstrate the validity of the proposed model and to illustrate its application to a variety of interconnect structures.
2015
We present a new model for predicting the delay, current & power in a CMOS Inverter. These delays, current & power are three major issues in design & synthesis of VLSI circuits, which depends on many other design parameter. In this paper we have used Tanner technology which deals with channel length in the order of 25 nm or even less. And simulation results are taken for different technology (32nm, 45nm) with the help of Tanner (Tspice) simulation tool. The propagation delay time determine the input to output signal delay during the high to low and low to high transitions of the output, respectively.
IEEE Journal of Solid-State Circuits, 1998
In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used. The final results are in excellent agreement with SPICE simulations.
IEEE Transactions on Communications, 1992
~~~ io = ion til7, \ _ _ -----I __:---.__ r-Abstract-Presented is a two-parameter model of line loss in a[dB/km] which the frequency dependence of loss is determined by way of the loss at the selected frequency and the conductor diameter. The and is model much quite better faithfully than the represents often used the Jf; actual model. loss of the line,
TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region, 2003
This paper proposes a new method to formulate the transistor sizing problem as a geometric programming by using a modified I-V model in the power-delay product (PDP), for sub micron and deep sub micron CMOS inverter circuit. The design objective and constraints are modeled as posynomial functions of the design variables. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (0.25-µm) results. Further the approach has been extended to predict the transistor sizing for deep submicron (0.09-µm) CMOS inverter.
Solid State Circuits Technologies, 2010
System-on-a-chip (SoC) has become possible since a great number of circuit elements can be integrated into a single chip by the miniaturization technologies for Si CMOS. Network-on-Chip (NoC) has been investigated actively, and it is expected to be a new approach for designing the communication subsystems of SoC (Lee et al., 2008). Enormous circuit blocks are loaded onto the NoC, and on-chip networks like local area networks (LANs) in the NoC communicate among these circuit blocks. Since the performance of the NoC is strongly affected by on-chip networks, the construction of efficient on-chip communications infrastructures will be increasingly significant. Some of the important characteristics for on-chip interconnects are bandwidth, latency, and power. In particular, power saving technologies are very important in realizing Green IT (in-formation technology). Power dissipation in on-chip networks mainly occurs at interconnects due to the increase of wiring resistance and capacitance. A significant issue is that power consumption of conventional on-chip interconnects, i.e. so-called RC lines, is proportional to the signal frequency; hence, it is very difficult to reduce energy dissipation per bit. Given the recent trend of high-speed signaling, we have to solve this problem and offer some good solutions. One solution is the use of copper lines and low-k dielectric, and these techniques have been widely applied and reduce power consumption for transmitting signals. However long interconnects still consume large power as in the case of RC lines. Another solution is the introduction of on-chip transmission line interconnects (TLIs). The applications of TLIs have been widely demonstrated. Modulation (Chang et al., 2003), pulsedcurrent-mode (
2015
─ An accurate high frequency small signal model for MOS transistors is presented. In the proposed model, by considering the layout of the MOS transistor, it is considered as a three-conductor transmission line. Then, a set of current-voltage equations are derived for the structure using the transmission line theory. These coupled equations are solved by the Finite-Difference Time-Domain (FDTD) technique in a marching-in-time process. To verify the model, the scattering parameters of a 0.13 m transistor are extracted from the time domain results over the 1–100 GHz frequency band and compared with the results obtained from the available models and commercial simulator. The suggested model can be useful in design of various types of high frequency integrated circuits. Index Terms ─ CMOS technology, distributed analysis, FDTD method, MOSFET model, transmission line model.
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