A CMOS Two-Element 170-GHz Fundamental-Frequency Transmitter With Direct RF-8PSK Modulation

International Journal of Electrical and Computer Engineering (IJECE), 2017

This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler driven by a two-way D-band power amplifier (PA). Simulation results show that the two-way D-band PA obtains a peak gain of 21.6 dB over a-3 dB bandwidth from 132 GHz to 159 GHz. It exhibits a saturated power of 7.2 dBm and a power added efficiency (PAE) of 2.3%, all at 150 GHz. The CS based doubler results in an output power of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC power of 205.8 mW from a 0.9 V supply voltage while it occupies an area of 2.1 mm 2 .

This article presents a dual-band millimeter-wave front end in 45-nm CMOS silicon-on-insulator (SOI) for 5G applications. The front end is composed of a low-noise amplifier (LNA), power amplifier (PA), and a single-pole doublethrow (SPDT) switch. A double-tuned PA is used and is based on a two-stage stacked amplifier with a reconfigurable load using SOI switches, so as to achieve an optimal load for both 28-and 39-GHz 5G NR bands. A wideband series-shunt switch is also developed with high power handling (P1dB > 22 dBm) and <1-dB insertion loss at 20-40 GHz. In the receive mode, the front end has a measured peak gain of 19.3 dB with a 3-dB bandwidth of 19.7-40 GHz, a noise figure (NF) < 4 dB at 18-40 GHz, and an IP1dB of 19 to 16 dBm. In the transmit mode and for lowband operation, the peak gain is 17.6 dB with a 3-dB bandwidth of 22.7-30.8 GHz. The P sat is >18.8 dBm and the peak PAE is 18% at 24-30 GHz and includes the switch loss and compression. For high-band operation, the gain at 36-40 GHz is 13.6 ± 1.5 dB with P sat > 18 dBm. To the best of our knowledge, this is the first front end that covers both the 24-28-and 37-40-GHz 5G bands with high output power and low-NF. Application areas are in multistandard base stations and small cells. Index Terms-5G, 45-nm CMOS silicon-on-insulator (SOI), front end, high efficiency, high power, low noise figure (NF), millimeter wave, wideband receiver. I. INTRODUCTION T HE 5G communication systems are being heavily investigated due to their potential to achieve high data rates in congested environments. At millimeter-wave frequencies, the path loss becomes severe and limits the link distances, and therefore, 16-to 512-element phased arrays are used for directional propagation and increased effective isotropic radiated power (EIRP). With an N × N antenna system, the EIRP is increased by 20log(N) compared with a single-channel transmitter, and the power per element becomes moderate even high EIRP levels. Most millimeter-wave systems operate at an Manuscript

IEEE Journal of Solid-State Circuits

This article introduces a four-element 300-GHzband bi-directional phased-array transceiver (TRX). The TRX utilizes the same antenna, signal path, and local oscillator (LO) circuitry to operate either in transmitter (TX) mode or receiver (RX) mode. The TX mode adopts the outphasing technique to increase the average output power for higher order modulation schemes by utilizing the two mixers that are connected directly to the antenna in a mixer-last fashion. The two signal paths also enable the canceling of the LO feed-through (LOFT). The RX mode also benefits from the LOFT cancellation technique to suppress the LO emission, which is a common issue of the mixer-first RXs. The RX has a separate Hartley operation mode to reject the image signal coming from the TX. The TRX chip was implemented using CMOS 65-nm process, and a four-element phased array was implemented by stacking liquid crystal polymer (LCP) flexible printed circuit boards (PCBs). The stacked structure provides the required narrow antenna pitch at the 300-GHz band. The measured beam angle range is from

IEEE Transactions on Microwave Theory and Techniques, 2013

This paper presents a four-element-band phased-array transmitter in 0.13-m CMOS. The design is based on the all-RF architecture and contains a 5-bit phase shifter (lowest bit is used as a trim bit), 4-bit gain control (to reduce the rms gain error), and power amplifiers capable of delivering a of 13.5 dBm per channel at 8.5-10.5 GHz. The chip can be used in the linear mode for communication systems and in the saturated mode for frequency-modulated continuous-wave radar systems, and therefore, extensive analysis is done on the phase shifter distortion versus input power. Spectral regrowth and error vector magnitude measurements indicate that the chip can support at least 20-MSym/s quadrature phase-shift keying and binary phase-shift keying modulation at an output power of 5 dBm per channel. Packaging techniques based on chip-on-board and quad flat no-lead (QFN) modules have been implemented with the four-channel chip, and both show a nearest neighbor coupling of 30 dB at 8-10 GHz, limited by bond-wire coupling. The chip dimensions are 2.9 3.0 mm and it consumes 870 mW from 2and 3-V power supplies.

2009

This paper reviews recent research conducted at the University of Toronto on the development of imaging and radio transceivers in CMOS, aimed at operation in the 100-GHz to 200-GHz range. Two receivers fabricated in 65-nm GPLP CMOS technology are described. The first is a 90-100 GHz IQ receiver with 7-dB noise figure, 10.5-dB downconversion gain and fundamental frequency VCO. The second receiver has a double-sideband architecture and operates in the 135-145 GHz range and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer and a dipole antenna.

2021 IEEE MTT-S International Microwave Symposium (IMS)

Fully-integrated 200 GHz direct-conversion transmitter and receiver ICs in InP-HBT process are presented. The transmitter exhibits > 20 dB conversion gain for 190-217 GHz, with 16.5 dBm / 15.3 dBm saturated output power at 195 GHz / 200 GHz, consuming 1,250 mW. The receiver has >15dB conversion gain over 190-213 GHz, 825 mW dissipation, and 7.7-9.3 dB noise figure over 200-212 GHz. An LO phase shifter enables sets of these ICs to form phased-array transceivers. Keywords-millimeter wave integrated circuits, THz integrated circuits, direct conversion, InP HBT.

2013 IEEE International Symposium on Phased Array Systems and Technology, 2013

With the rapid development of the applications in short range communication, phased-array receiver working at 24 GHz can provide enhanced gain performance at desired transmission direction. Also there is the wide signal bandwidth, i.e. 250 MHz free licensed spectrum at this frequency. In the phasedarray front-end, the key component is the phase shifter, which decides the tuning resolution of beam-forming. The challenge of the design work comes from the low-power, low-noise and lowcost requirement. This paper explores the design procedure of a Vector Modulation Phase Shifter (VMPS), consisting of a 90 • hybrid, a variable gain amplifier and the Wilkinson combiner. The variable gain amplifier is fabricated in 90nm complementary metal-oxide-semiconductor technology, and the passive hybrid and the Wilkinson combiner are designed on the printed circuit board with RO4003 substrate. After combining the measurement results of each block, the VMPS shows 45 • phase shifts with 7 • phase error, and 9 mW consumption.

— This paper presents the first phased array transceiver operating from 71 to 86 GHz using injection-locked oscillators (ILOs) for phase shifting. A folded-cascode ILO is proposed to extend the locking range of an array of oscillators. Frequency multiplication covers a 10-GHz tuning range with 23-dB power gain. Each ILO path covers more than ±300° and exhibits low amplitude variation with respect to phase shift range (<1 dB) and excellent isolation and amplitude error (<0.5 dB) between array elements. A wideband, bidirectional RF front end delivers 10-dBm maximum output power with more than 20-dB conversion gain over the 3-dB bandwidth in the transmit (TX) mode and a minimum 9.5-dB noise figure with more than 20-dB conversion gain in the receive (RX) mode. Low phase noise is demonstrated in the ILO approach over the phase tuning range with −112 dBc/Hz at 1-MHz offset and phase noise variation for different phase shift states under 2.5 dB, corresponding to less than 2° phase error. Array patterns demonstrate the wide scan range, and dynamic measurements show that the transmitter supports up to 6-Gb/s data rate with 256 QAM. The chip has 3.4 × 2.1 mm 2 area implementing in the 90-nm BiCMOS technology and consuming 386.4 mW in the TX mode and 286 mW in the RX mode per element. Index Terms— Bidirectional transceivers, injection-locked oscillator (ILO) phase shifter, millimeter-wave, multiplier, 90-nm SiGe BiCMOS, scalable phased array, wideband.

2019

The millimeter-wave (mmW) range of the electromagnetic spectrum, which includes frequencies from around 30 to 300 GHz, offers some unique propagation properties and a vastly available bandwidth. Therefore, it enables relieving the overpopulated lower part of the spectrum and satisfying the huge data demands from the users. It also allows the proliferation of new applications such as automotive radar, high-speed personal area networks, and noninvasive surveillance, just to name a few of them. In addition, while in the past working at mmW frequencies was only possible using III-V technologies, the successive scaling of silicon-based technologies like CMOS and BiCMOS has brought mmW circuit designs and applications to the mass market. Many excellent books on RFIC design using silicon technologies have been published, and with the aid of the existing powerful simulation software, one can design RF circuits with acceptable performance quickly and with moderate effort. However, when it comes to mmW circuit design, succeeding is not that simple. Semiconductor technologies are struggled to their limits in terms of operation frequency and available power, and PVT variations can greatly jeopardize the device performance. This is especially critical in transmitters, which need to provide enough output power to compensate for the high path loss, while at the same time maintaining the bandwidth in a power-efficient way. Furthermore, the wide bandwidth and data throughput required by current communication applications are also pushing digital design to the limits in terms of sampling speed and power consumption, and it is, therefore, not straightforward to use DSP techniques to compensate for the RF imperfections. In this book, we present an approach to mmW circuit design using advanced RF circuit design and digital processing techniques at the same time. This way, front-end architectures that balance the requirements of the RF and DSP blocks can be selected, and it is possible to sense the operating conditions of the critical circuits in order to compensate for the imperfections and bring the performance back to the vii optimum values. All the design stages of a typical mmW transmitter are covered, from the link budget analysis to transistor-level design and system tests using high-order modulated signals. The procedure to present the different designs and subsystems is to first explain the concepts from a theoretical point of view, and then apply them to the design of an E-band 10-Gbps BiCMOS-integrated transmitter. Some previous knowledge of semiconductor devices, transmission systems, and signal theory is assumed from the reader, although theoretical concepts and expressions are introduced when required for the discussion. These prior concepts are sometimes explained in a rather intuitive way, as our intention is to focus more on the actual scope of the book: revisiting the traditional approaches and proposing new techniques appropriate for wideband and power-efficient mmW IC design. Nevertheless, references where the information is more thoroughly explained are provided, in case the reader feels some concepts are oversimplified or seeks further explanation. Chapters are intended to be self-contained, each with its own introduction and conclusion sections, so that most of them can be read independently. Nevertheless, they are ordered according to the natural design flow, starting from the system-level analysis and going down to the transistor-level design. Chapter 1 is a general introduction to millimeter waves, explaining the motivations to explore this frequency range and the technologies that make it possible. In Chap. 2, considerations for the link budget and system-level analysis are given, whereas Chap. 3 analyzes the typical imperfections that degrade the performance of mmW communication systems, showing how they affect the signal. One of the imperfections that most affects wideband mmW systems is transmitter I/Q imbalance. It is typically addressed as non-frequency selective, but in wideband and spectrally efficient systems this assumption is no longer true and different correction techniques need to be applied. Therefore, Chap. 4 is dedicated to I/Q imbalance analysis and compensation. The rest of the chapters deal with the circuit-level design of the core blocks of an integrated mmW transmitter front-end. Chapter 5 outlines a design methodology for BiCMOS mmW integrated circuits. Chapters 6-8 deal with the design of upconverters, power amplifiers, and power detectors, respectively. Different alternatives and trade-offs for the design of these blocks are first presented, and then design examples of real implemented circuits are given. These circuits are designed aiming at wideband operation and transmission of multi-Gbps signals, and they allow implementing the digitally assisted correction, self-healing and built-in integrated self-test (BIST) techniques outlined in the previous chapters. Finally, Chap. 9 presents an integrated and digitally assisted BiCMOS transmitter, which is able to transmit at 10-Gbps speeds in the E-band. The techniques presented in the previous chapters have been applied to its design. This book comes after years of research in the field of wideband-integrated mmW transmitters for high-speed communications. We have tried to gather all the wisdom and experience we have acquired in the way, because we believe that viii Preface Preface ix Government through its Ph.D. scholarship program, and the European Commission through its FP7 Research Program. xi Contents xv xvi Contents

2013 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2013), 2013

In this paper, we present a transmitter operating in the 210-227 GHz in 90-nm CMOS, based on a Colpitts VCO. The third harmonic of the generated VCO fundamental signal is coupled to an on-chip dipole antenna. The silicon substrate of the CMOS chip is thinned from 280 µm to 80 µm in order to improve the performance of the transmitter in terms of effective isotropic radiated power (EIRP) and directivity. The transmitter achieves an EIRP of +2.8 dBm at 217 GHz and a directivity of about +13.1 dBi with a total power radiated of -10.3 dBm. The circuit consumes 134 mW of DC power and an area of 0.53 mm 2 .