A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2017

A four element, two channel Multiple-Input Multiple-Output (MIMO) phased array receiver at 15 GHz is designed and fabricated in 45nm CMOS SOI process. The receiver consists of two independent four-antenna phasedarrays for hybrid beamforming and MIMO processing in digital domain. Phase and amplitude control is based on RF IQ vector modulator (VM) at carrier frequency. Measured downconversion gain and noise figure (NF) of one path are 23 dB and 5.4dB, respectively, giving estimated 3.4 dB NF for the IC when simulated PCB and matching losses are taken into account. 1 dB compression and IIP3 points are −37 dBm and −28 dBm, respectively. One phased array consumes 486 mW DC power from 1.2V power supply. Total chip area is 5.69 mm2.

IEEE Transactions on Microwave Theory and Techniques, 2000

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-m CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of +0.1 dBm.

2011 IEEE Radio Frequency Integrated Circuits Symposium, 2011

A Digital RF receiver front-end with wideband operation capability is presented for m-WiMAX application. By employing sampling mixer and discrete-time filter, the receiver operates in charge domain. In addition to flexibility of the discrete-time (DT) filter, the new Non-Decimation Finite Impulse Response (FIR) filter can be cascaded to a conventional FIR filter. And we can easily increase the order of the sinc n-type filtering response and achieve wideband signal process capability. The designed receiver front-end is implemented by IBM 0.13-RF CMOS process. The chip satisfies the m-WiMAX specification with 26.63mA from a 1.5-V supply voltage for the total system.

IEEE Journal of Solid-State Circuits, 2018

This paper presents a "fully-connected" hybrid beamforming receiver that independently weights each element in an antenna array prior to separate downconversion chains that output independent baseband streams. A receiver architecture is introduced which implements RF-domain complex-valued Cartesian-weighting, RF-domain combining and multi-stream heterodyne complex-quadrature downconversion. Each RF-domain Cartesian weight is implemented by a pair of 5bit digitally-controlled programmable gain amplifiers (PGA), whose outputs are combined with the weighted signals from other antennas prior to complex-quadrature downconversion. Signal combination is performed by a wideband small-footprint distributed active combiner. A 25-30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams is designed in 65 nm CMOS. In each antenna path, the receiver achieves 34 dB conversion gain, 7.3 dB minimum noise figure, and 5 GHz of RF bandwidth. The entire receiver consumes 340 mW (equivalent to 27.5 mW per antenna per stream) including low-noise amplification, RF-domain beamforming, multi-stream downconversion and LO generation and distribution circuitry. The receiver occupies 3.86 mm 2 excluding pads, equivalent to 0.36 mm 2 per antenna per stream. Single-element characterization results are presented, along with characterization of several spatial processing techniques including interference cancellation (20 dB peak-to-null for two elements), simultaneous two-stream reception, and adaptivecodebook-search based beam-acquisition.

IEEE Journal of Solid-state Circuits, 2007

802.11n is the latest offering from the IEEE standard committee tasked with enabling and enhancing WLAN systems. This standard utilizes several techniques to offer a much larger rate versus range than the legacy WLAN systems. A single-chip multiband direct-conversion CMOS MIMO transceiver (2 2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the draft 802.11n standard and achieves PHY rates of 270 Mb/s. The receivers and transmitters achieve an EVM of better than 41 dB (0.9%) and 40 dB (1.0%) operating in legacy g and a modes, respectively.

IEEE Transactions on Microwave Theory and Techniques, 2020

Active control of interference is necessary with increased cell density, more complicated environmental reflections, and coexistence of multiple networks for next-generation wireless communications. The existing radio receiver architectures for spatial interference cancellation (SpICa) are limited by the spatial nulls created by a phased-antenna array (PAA) and cannot cover wide modulated bandwidths (BWs). We propose a discrete-time-delay-compensating technique for canceling spatial interferences with wide modulated BWs to reduce the dynamic range requirement for the data converter. Integral to the proposed circuit is a switched-capacitor-based multiplyand-accumulate processor that incorporates a reconfigurable phase interpolator and time interleaver for precise digitally tunable delays and multiplication of the input signal to an orthogonal matrix. The digital time interleaver enables 5-ps resolution with a reconfigurable range up to 15 ns. The measured results demonstrate greater than 35-dB SpICa over 80-MHz modulated BWs in the 65-nm CMOS with 52 mW of power consumption.

A digital RF receiver front-end employing a DT filter is proposed for application to m-WiMAX & The SAW-less receiver architecture, where the large out-of-band interferer can be rejected selectively by using a scalable frequency response property of FIR filter. In addition to the flexibility of the DT filter, the new non-decimation finite impulse response (NDF) filter can be cascaded to a conventional FIR filter without the decimation effect. Thus, we can easily increase the order of the function-type filtering response and the signal processing bandwidth and the designed receiver front-end is implemented using an IBM 130-nm RF CMOS process. The fabricated chip satisfies the m-WiMAX specification of an 8.75 MHz channel bandwidth and the total system power consumption is 26.63 mA from a 1.5-V supply voltage. The chip shows unwanted blocker rejection over 80 dB, with good linearity of +3.94 dB IIP3.

IEEE Journal of Solid-state Circuits, 2006

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm 2 .

IEEE Journal of Solid-state Circuits, 2008

This paper reports a 6-to-18 GHz integrated phasedarray receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5 and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB.

2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019

This paper discusses early results associated with a fully-digital direct-conversion array receiver at 28 GHz. The proposed receiver makes use of commercial off-the-shelf (COTS) electronics, including the receiver chain. The design consists of a custom 28 GHz patch antenna sub-array providing gain in the elevation plane, with azimuthal plane beamforming provided by real-time digital signal processing (DSP) algorithms running on a Xilinx Radio Frequency System on Chip (RF SoC). The proposed array receiver employs element-wise fully-digital array processing that supports ADC sample rates up to 2 GS/second and up to 1 GHz of operating bandwidth per antenna. The RF mixed-signal data conversion circuits and DSP algorithms operate on a single-chip RF SoC solution installed on the Xilinx ZCU1275 prototyping platform.