A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

This paper presents a W-band receiver chipset for passive millimeter-wave imaging in a 65 nm standard CMOS technology. The system comprises a direct-conversion receiver front-end with injection-locked tripler and a companion analog back-end for Dicke radiometer. The receiver design addresses the high 1/f noise issue in the advanced CMOS technology. An LO generation scheme using a frequency tripler is proposed to lower the PLL frequency, making it suitable for use in multi-pixel systems. In addition, the noise performance of the receiver is further improved by optimum biasing of transistors of the detector in moderate inversion region to achieve the highest responsivity and lowest NEP. The front-end chipset exhibits a measured peak gain of 35 dB, 3 dB BW of 12 GHz, NF of 8.9 dB, while consuming 94 mW. The baseband chipset has a measured peak responsivity ( ) of 6 KV/W and a noise equivalent power (NEP) of 8.54 pW Hz 1 2 . The two chipsets integrated on-board achieve a total responsivity of 16 MV/W and a calculated Dicke NETD of 1K with a 30 ms integration time.

IEEE Transactions on Microwave Theory and Techniques

A high-resolution frequency-modulated continuous wave imaging radar for short-range applications is presented. A range resolution of about 1 cm is achieved with a bandwidth of up to 16 GHz around 160 GHz. In order to overcome losses and large tolerances on a printed circuit board (PCB), eight coherently coupled monolithic microwave integrated circuits (MMICs) are used, each with one transmit and receive antenna on-chip and each representing a single-channel radar system. The signals on the PCB are below 12 GHz, which facilitates fabrication and enables a design with low-cost substrates. The MMIC comprises a phase noise (PN)-optimized architecture with a fully integrated on-chip frequency synthesizer. Due to partly uncorrelated PN between the frequency synthesizer components, the noise level is increased in bistatic radar measurements between two different MMICs, which is explained by a thorough PN analysis. Timedivision multiplexing is used to realize a multiple-input multipleoutput system with a virtual array of 64 elements and an angular resolution better than 1.5 • for the designed array. The positioning tolerances of the MMICs are included into the design resulting in a robust array design. The high-resolution radar performance is proven by imaging radar measurements of two exemplary scenarios.

2009

This paper reviews recent research conducted at the University of Toronto on the development of imaging and radio transceivers in CMOS, aimed at operation in the 100-GHz to 200-GHz range. Two receivers fabricated in 65-nm GPLP CMOS technology are described. The first is a 90-100 GHz IQ receiver with 7-dB noise figure, 10.5-dB downconversion gain and fundamental frequency VCO. The second receiver has a double-sideband architecture and operates in the 135-145 GHz range and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer and a dipole antenna.

We describe a novel low noise amplifier (LNA) fabricated in silicon germanium with a narrow bandwidth at 95 GHz with high gain and medium output power. The amplifier will be used as the part of the front end receiver in a passive millimeter wave (mmW) imager based on optical up-conversion. This allows for a highly sensitive, real-time, and economical millimeter wave imaging system.

2011 11th Mediterranean Microwave Symposium (MMS), 2011

Majority of the reported millimeter-wave (MMW) imaging systems are constructed on the basis of conventional waveguide technology as this technology is known to provide the best performance over higher frequency ranges. This paper proposes and presents an alternative platform of technology based on the substrate integrated waveguide (SIW) technology. Early results in the development of an SIW passive millimeterwave imaging system are reported and discussed in this work. This technology presents many advantages over the conventional waveguide technology such as lower cost, smaller size, integrability with printed circuit board (PCB) technologies, compactness, as well as low interference susceptibility. An SIW passive imaging system operating at 35 GHz intended for concealed weapon detection is demonstrated at its early stage. It consists of a mechanically scanning reflector antenna, an SIW direct receiver and a computer running data acquisition software. The direct receiver presents a 1.5 GHz bandwidth centered at 35 GHz, 2.7 dB noise figure, and 48 dB gain. It was built upon interconnecting SIW sub-circuits in a LEGO manner which is appropriate for system prototyping. Resulting images for different scenarios are presented and the system operability is demonstrated.

A W-band direct-detection-based receiver front-end for millimeter-wave passive imaging in a 0.18m BiCMOS process is presented. The proposed system is comprised of a direct-detection front-end architecture employing a balanced LNA with an embedded Dicke switch, power detector, and baseband circuitry. The use of a balanced LNA with an embedded Dicke switch minimizes front-end noise figure, resulting in a great imaging resolution. The receiver chip achieves a measured responsivity of 20-43 MV/W with a front-end 3-dB bandwidth of 26 GHz, while consuming 200 mW. The calculated NETD of the SiGe receiver chip is 0.4 K with a 30 ms integration time. This work demonstrates the possibility of silicon-based system-on-chip solutions as lower cost alternatives to compound semiconductor multi-chip imaging modules.

IEEE Transactions on Microwave Theory and Techniques, 2013

An integrated frequency agile quadrature-band receiver is presented in this paper. The complete receiver is realized in a commercial m SiGe:C technology with an of 170/250 GHz. The receiver covers the two point-to-point communication bands from 71 to 76 GHz and from 81 to 86 GHz and the automotive radar band at 77 GHz. A wide tuning range modified Colpitts oscillator provides a local oscillator (LO) tuning range 30. A two-stage constant phase RC polyphase network is implemented to provide wideband in-phase quadrature LO signals. The measured phase imbalance of the network stays below 8 over the receiver's frequency range. In addition the chip includes a wideband low-noise amplifier, Wilkinson power divider, down conversion mixers, and frequency prescaler. Each of the chip's receiver I/Q paths shows a measured conversion gain above 19 dB and an input referred 1-dB compression point of 22 dBm. The receiver's measured noise figure stays below 11 dB over the complete frequency range. Furthermore, the receiver has a measured IF bandwidth of 6 GHz. The complete chip including prescaler draws a current of 230 mA from a 3.3-V supply, and consumes a chip area of 1628 m 1528 m. Index Terms-band, low-noise amplifier (LNA), polyphase, quadrature generation, voltage-controlled oscillator (VCO), wideband receiver. I. INTRODUCTION A RAPID growth can be observed in the field of millimeterwave circuits and systems, which is closely related to the ongoing evolution in silicon technology. There are several important applications allocated within the-band, including short-range wireless high-definition (HD) video transmission and industrial radar [1] at 60-GHz last-mile wireless point-topoint high data-rate communication at the two bands of (lower) Manuscript

Existing SAR systems are often limited in resolution by their small bandwidth of below 10 GHz. In this contribution an ultra-wideband 80 GHz FMCW radar sensor for SAR imaging with 25.6 GHz bandwidth is presented. It is based on a custom low-power SiGe-MMIC including all high frequency components, using a nested PLL concept in combination with off-the-shelf PLL synthesizer ICs. In single direction radar measurments, a resolution of 8.09 mm is shown. Additionally, results of SAR measurements with a point target show that a good spatial resolution of 12.0 mm x 8.1 mm (Tukey window, α = 0.25, −6 dB width) is achieved. Furthermore, high resolution SAR images of a bike acquired with the sensor are presented.

Analog Integrated Circuits and Signal Processing, 2018

This paper presents the design of a millimeter-wave wideband receiver front-end in a 0.13 lm SiGe BiCMOS technology for phased array applications. The receiver front-end is suitable for a phased array time-division duplexing communication system where both the transmitter and the receiver share the same antenna. The monolithic microwave integrated circuit front-end comprises of quarter-wave shunt switches, a low-noise amplifier (LNA), an active phase shifter and a buffer amplifier. The quarter-wave shunt switch is designed using reverse-saturated SiGe HBTs. The transformer-based LNA utilizes a common-emitter amplifier at the first stage and a cascode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The designed switch is incorporated in the input matching network of the LNA. The active phase shifter consists of variable gain amplifiers driven by a polyphase filter-based quadrature generator. The receiver front-end achieves a measured gain of 18.5 dB and a noise figure of 9 dB with a 3 dB bandwidth of 23 GHz from 56 to 79 GHz. The receiver phase can be tuned continuously from 0 to 360. An output referred 1-dB compression point of À 7.4 dBm is achieved at 70 GHz. The receiver consumes 116 mW of DC power and occupies a core area of 1800 lm  475 lm.

IEEE Transactions on Instrumentation and Measurement, 2012

We have developed two passive millimeter-wave imagers for terrestrial remote sensing: one is an integrated imaging and spectroscopy system in the 146–154-GHz range with 16 channels of 500-MHz bandwidth each, and the other is a single-channel dual-polarized imaging radiometer in the 70–100-GHz range. The imaging in both systems is implemented through translation of a 15-cm Gaussian dielectric imaging lens. We

International Journal of Microwave and Wireless Technologies, 2011

A 160-GHz SiGe-HBT (Heterojunction Bipolar Transistor) down-conversion receiver front-end for use in active millimeter-wave imaging arrays and D-band communication applications is presented. The monolithic front-end consists of a three-stage low-noise amplifier providing 24 dB of gain and a Gilbert-cell mixer capable of operating from a −8-dBm LO signal. A fully differential architecture compatible with balanced on or off-chip antennas is used to avoid the need for on-chip baluns in antenna-integrated applications. The implemented downconversion front-end consumes 50 mA from a 3.3 V supply and requires a 0.1 mm2 die area (excl. pads) per channel. With a 160-GHz input signal and an Intermediate Frequency (IF) of 1 GHz, the implemented front-end yields a 25-dB conversion gain, a −30-dBm input compression point, and a 9-dB/7-dB (with/without auxiliary on-chip input balun) system noise figure.

IEEE Communications Magazine, 2000

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2011

This paper presents a 65-nm CMOS 8-antenna array transmitter operating in 117-130-GHz range for short range and portable millimeter-wave (mm-wave) active imaging applications. Each antenna element is a new on-chip antenna located on the top metal. By using onchip transformer, pulse output of each resistor-less mm-wave pulse generators (PG) are sent to each integrated antenna. To adjust pulse delays for the purpose of pulse beam-forming, a 7-bit digitally programmable delay circuit (DPDC) is added to each of PGs. Moreover, in order to dynamically adjust pulse delays among eight SW's outputs, we implemented onchip jitter and relative skew measuring circuit with 20-bit digital output to achieve cumulative distribution (CDF) and probability density (PDF) functions from which DPDC's input codes are decided to align eight antenna's output pulses. Two measured radiation peaks after relative skew alignment are obtained at (θ; φ) angles of (−56 • ; 0 •) and (+57 • ; 0 •). Measurement results shows that beam-forming angles of the fully integrated antenna array can be adjusted by digital input codes and by the on-chip skew adjustment circuit for active imaging applications.

IEEE Journal of Solid-State Circuits, 2012

This paper presents a terahertz (THz) transmitter (Tx) and receiver (Rx) chipset operating around 400 GHz in 0.13-m SiGe BiCMOS technology. The Tx chip consists of a voltage-controlled oscillator, a buffer, a modulator, a power amplifier, a frequency tripler, and a substrate integrated waveguide (SIW) antenna. This antenna has an additional high-pass filtering characteristic to suppress the unwanted fundamental and second harmonic signals by 50 and 30 dB, respectively. The Rx chip includes a proposed reconfigurable SIW antenna and a novel two-mode subharmonic mixer with 5-dB reduction of conversion loss. The Rx chip consumes 50 nA from a 1.2-V supply. The measurement results of the Tx and Rx chips and a back-to-back test of the Tx/Rx chipset show the feasibility and pave the way of implementing a fully integrated THz system in silicon technology for mass production.

HAL (Le Centre pour la Communication Scientifique Directe), 2014