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2008, 2008 IEEE Custom Integrated Circuits Conference
The design of a millimeter-wave dual-band phaselocked frequency synthesizer in a 0.18µm SiGe BiCMOS technology is presented. All circuits except the voltage controlled oscillators (VCOs) are shared between the two bands. A W-band divide-by-3 frequency divider is used inside the loop after the VCOs to simplify division-ratio reconfiguration. The 0.9mm 2 synthesizer chip exhibits a locking range of 23.8-26.95/75.67-78.5GHz with a low power consumption of 50-75mW from a 2.5V supply. The closed-loop phase noise at 1MHz offset from the carrier is less than -100dBc/Hz in both bands. The proposed frequency synthesizer is suitable for integration in directconversion transceivers for K/W-band automotive radars and heterodyne receivers for 94GHz imaging applications.
2009
Abstract Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop.
2007 IEEE Compound Semiconductor Integrated Circuits Symposium, 2007
We present a fully integrated phase-locked loop tunable from 17.5 GHz to 19.2 GHz fabricated in a 0.25 µm SiGe BiCMOS technology. The measured phase noise is below -110 dBc/Hz at 1 MHz offset over the whole tuning range. Based on an integer-N architecture, the synthesizer consumes 248 mW and occupies a chip area of 2.1 mm 2 including pads. Quadrature outputs at quarter of the oscillator frequency are produced, which are required in a sliding-IF 24 GHz transceiver. Possible applications include wireless LAN as well as satellite communication. The measured phase noise is the lowest among previously published Si-based integrated synthesizers above 12 GHz. Index Terms -Phase-locked loop, wireless LAN, SiGe, BiCMOS, phase noise, 24 GHz.
Progress In Electromagnetics Research C, 2014
In this paper, a 42 GHz frequency synthesizer fabricated with 0.13 µm SiGe BiCMOS technology is presented, which consists of an integer-N fourth-order type-II phase locked loop (PLL) with a LC tank VCO and a frequency doubler. The core PLL has three-stage current mode logic (CML) and five stage true single phase clock (TSPC) logic in the frequency divider. Meanwhile, a novel balanced common-base structure is used in the frequency doubler design to widen the bandwidth and improve the fundamental rejection. The doubler shows a 41% fractional 3 dB bandwidths with a fundamental rejection better than 25.7 dB. The synthesizer has a maximum output power of 0 dBm with a DC power consumption of 60 mW. The worst phase noise at 100 kHz, 1 MHz and 10 MHz offset frequencies from the carrier is −71 dBc/Hz, −83 dBc/Hz and −102.4 dBc/Hz, respectively.
IEEE Journal of Solid-State Circuits, 2002
A 2.5-GHz/900-MHz dual fractional-/integerfrequency synthesizer is implemented in 0.35-m 25-GHz BiCMOS. A 16 fractional-synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip 16 modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of 88 dBc/Hz for 2.47-GHz output frequency and 98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply.
IEEE Transactions on Microwave Theory and Techniques, 2012
Two monolithically integrated W-band frequency synthesizers are presented. Implemented in a 0.18 m SiGe BiCMOS with of 200/180 GHz, both circuits incorporate the same 30.3-33.8 GHz PLL core. One synthesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1 GHz and the other employs a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5 GHz from 90.9-101.4 GHz, respectively. The measured RMS phase noise for ILFT-and HBFT-based synthesizers are 5.4 and 5.5 (100 kHz to 100 MHz integration), while phase noise at 1 MHz offset is and dBc/Hz, respectively, at 96 GHz from a reference frequency of 125 MHz. The measured reference spurs are dBc for both prototypes. The combined power consumption from 1.8-and 2.5-V is 140 mW for both chips. The frequency synthesizer is suitable for integration in millimeter-wave (mm-wave) phased array and multi-pixel systems such as W-band radar/imaging and 120 GHz wireless communication.
Analog Integrated Circuits and Signal Processing, 2016
A highly linear and fully-integrated frequencymodulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57-64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (RD) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than −80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is 2:04 mm 2 , and the total power consumption is 280 mW.
Microwave and Optical Technology Letters, 2013
This article presents a 24/77-GHz transmitter chipset for automotive radar sensors implemented in a 160/175-GHz f T /f max SiGe BiCMOS technology. The chipset adopts a dual-band architecture consisting of a 24-GHz section for ultra-wideband short-range radar operation, which is also exploited to drive the 77-GHz long-range radar transmitter front-end. The proposed design adopts a single 24-GHz frequency synthesizer to implement both radar operation modes. The transmitter chipset is able to deliver a maximum output power of 3 dBm and 12 dBm at 24 GHz and 77 GHz, respectively. The 24-GHz transmitter demonstrates to operate with pulse widths of 0.5 ns and 1 ns in compliance with the transmission mask designed by ETSI. The 77-GHz transmitter exhibits a power gain of 20 dB, an output power of 12 dBm, and an output referred 1-dB compression point of 9.5 dBm, while drawing 155 mA from a 2.5-V supply voltage. V
Analog Integrated Circuits and Signal Processing, 2014
A 2.5 GHz direct digital frequency synthesizer (DDS) in 0.18 lm CMOS is presented. This DDS has a 32 bit phase word and uses an optimized excess-four Coordinated Rotation Digital Computer (CORDIC) arithmetic to achieve phase to amplitude conversion (SFDR as 113 dB). A time interleaved architecture is used to achieve 2.5 GHz high speed. Fundamental principle of CORDIC and four practical considerations in circuit implementation are also presented. This 2.5 GHz DDS (with an embedded 14 bit current steering DAC) is implemented in a 0.18 lm CMOS technology, occupies 4.6 mm 9 4.2 mm including bond pads. Measured performance is SFDR [58 dB (spur cancelled) and narrowband SFDR[84 dB for output signal frequencies up to 1 GHz.
VLSI System on Chip …, 2010
This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15. 4 frequency synthesizer designed using 0.18 μm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 ...
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency for the synthesizer. Additionally, a hybrid circuit utilizing a new folded regime for the first-stage divider and the phase-rotating circuit is developed in the prescaler. Under full-speed operation, the QVCO with the frequency doubler and the divider can work from a 0.5-V supply, whereas the synthesizer dissipates 12 mW. At 9.1-GHz carrier frequency, the measured phase noise is −104.5 dBc/Hz from 1-MHz offset.
IEEE Journal of Solid-State Circuits, 2014
A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of-77.8 dBc/Hz (-82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32-303.36 GHz (7.9%).
IEEE Journal of Solid-State Circuits, 2004
The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as 70 dBc and the phase noise is lower than 116 dBc/Hz at 1 MHz over the whole tuning range.
2005 European Microwave Conference, 2005
This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL, for ISM band, with a new low power prescaler. This circuit is implemented in a 0.25 m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 170 mW and fulfills a 23.7 to 24.9 GHz frequency locking range, while exhibiting a phase noise of -100 dBc/Hz at 100 KHz from the carrier. The simulated PLL unity-gain bandwidth is 36 MHz, with a phase margin of 54 . The PLL uses a new latch-based prescaler (SRO) which exhibits a power dissipation of 0.68 GHz/mW.
IEEE Journal of Solid-State Circuits, 2000
A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-m SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic range (SFDR) of the DDFS is better than 48 dBc at low synthesized frequencies, decreasing to 45.7 dBc worst case at the Nyquist synthesized frequency for output frequency band (0-2.5 GHz). The DDFS consumes 460 mW at a 3.3-V supply and achieves a high power efficiency figure of merit (FOM) of 10.87 GHz/W. The chip occupies mm .
Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009
This paper presents a low-power/low-voltage frequency synthesizer for the frequency of 2.4 GHz, which were designed and fabricated in a standard 0.18 Pm CMOS process. This synthesizer is based on a Phase-locked Loop (PLL) with a integer divider in the feedback loop and for a voltage supply of only 1.8 V, it presents a total power consumption of 3.4 mW. The power consumptions for the Voltage-controlled oscillator, phase-frequency difference/charge-pump and for the divider are 2 mW, 1 mW, 420 PW, respectively. The PLL is very fast, e.g., it takes only 1.6 Ps to lock, which makes it a perfect companion for devices where frequency hops must be done very quickly.
International Journal of Infrared and Millimeter Waves, 1994
This paper is concerned with description of development of commercial millimeterwave frequency synthesizer promised by authors in previous paper . Synthesizer described has highest for commercial synthesizers at the moment frequency range 118 GHz -178 GHz and due to the use in it of Russian -made Backward Wave Oscillator (BWO) radiation source of the [2] type has continuous tunability range'as broad as 60 GHz and significant -from 3 to 10 m W -output power in the whole range covered. Minimal frequency step is 100 Hz. Synthesizer is fully microprocessor -or PC -(through IEEE-488) controlled. Mentioned are other members of this synthesizer family (37 -53 GHz, 53 -78 GHz, 78 -118 GHz) also now in production (general information about development of Russian frequency synthesizers from 1.07 GHz up to 118.1 GHz can be found in ). Possibility of further extension of frequency range up to 256 GHz in serial and up to 1 THz in laboratory versions (see )is considered.
Proceedings of the Int …, 2006
Due to development of both wireless communication users and communication line users, utilization of high-speed communications has become a vital essence. High speed digital microwave radios have a great contribution in wireless telecommunications. Having a different and high capacitance, these radios can transmit and receive data in point to point links in far distances up to 30 km. Considering the high rate of utilization such digital microwave radios have in lower bands, it is imperative to utilize such kind of radios in upper bandsfor accessing more channels. One of the radios that plays a significant role in communications is digital microwave radio 18 GHz. Through using a proper modulation in this band, transmitting data with high rate is achievable. In this paper, frequency synthesizer of this radio has been analyzed, designed and implemented. By applying proper changes, this synthesizer can be used as a frequency sweeper either. In this project in order to have a stable local oscillator and a good phase noise of output signal, a phase locked DRO was designed and implemented. This stable signal will be mixed with an L-band synthesized signal and it will generate signal in the band 17.7 GHz -19.7 GHz with step 0.25 MHz. The stable output signal of this synthesizer has a very good phase noise at 18 GHz. We have achieved to phase noise up to -88 dBc/Hz @10 kHz in 18 GHz which is a proper phase noise for using different modulations such as QPSK, 16QAM, 64QAM and...
16th International Conference on Telecommunications, ICT 2009, 2009
This paper presents a Phase-Locked Loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in the UMC RF 0.18 µm CMOS process. The PLL produces a set of different 16 digitally programmable frequencies in the [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback path. Simulations shown a total power consumption of 4.2 mW. Target applications are wireless sensors and microsystems applications that need RF transceivers for operation in the 5.7 GHz band.
The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.
The design and simulation of a 1.35 GHz CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based in a wideband PLL topology with a high frequency reference, giving as result low phase noise, fast switching time, a low divider ratio and a reduction in the chip area. Besides, the use of a novel charge-pump circuit with positive feedback and current reuse allows a further reduction in both, chip area and power consumption, making the structure desirable for high-frequency low-voltage phase-locked loops.
International Journal of Electronics and Electrical Engineering, 2014
A 1.1GHz phase-locked loop frequency synthesizer has been developed, designed and fabricated to study phase noise (PN) of the system. The system has been implemented by using a frequency synthesizer (ADF4002, Analog Devices), having a low noise digital phase frequency detector, a precision charge pump, a programmable reference divider (R divider) and a programmable feedback frequency divider (N divider). The charge pump, reference divider and phase frequency divider are programmed externally through a serial peripheral interface by writing to CLOCK, DATA and LATCH ENABLE control of the device. The system is interfaced to a personnel computer through an 8085 microprocessor via RS232 serial bus. This paper will give a brief outline of the hardware design, testing and study the PN of the system. Index Terms-phase-locked loop, loop filter, phase noise, OshonSoft Tulshi Bezboruah received the B.Sc. degree in physics with electronics from the University of Dibrugarh, India, in 1990 and the M.Sc. and Ph.D. degrees in electronics and radio physics from the
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